Product Specification
PE4305
Product Description
The PE4305 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 15.5 dB attenuation range in 0.5 dB steps,
and is pin compatible with the PE430x series. This 50-ohm RF
DSA provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4305 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4305 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
RF Input
50
Ω
RF Digital Attenuator
5-bit, 15.5 dB, DC – 4.0 GHz
Features
•
Attenuation: 0.5 dB steps to 15.5 dB
•
Flexible parallel and serial programming
interfaces
•
Latched or direct mode
•
Unique power-up state selection
•
Positive CMOS control logic
•
High attenuation accuracy and linearity
over temperature and frequency
•
Very low power consumption
•
Single-supply operation
•
50
Ω
impedance
•
Pin compatible with PE430x series
•
Packaged in a 20 Lead 4x4 mm QFN
Switched Attenuator Array
Parallel Control
Serial Control
5
Power-Up Control
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V
Parameter
Insertion Loss
2
BS
C
3
1
Control Logic Interface
Test Conditions
W
Frequency
O
IT
RF Output
LE
H
PE
T
4x4 mm 20-Lead QFN
Figure 2. Package Type
Minimum
DC
-
-
30
-
15
-
Typical
1.5
-
34
52
20
-
43
12
Maximum
4000
2.25
±(0.25 + 3% of atten setting)
not to exceed ± 0.4 dB
-
-
-
1
E
Units
MHz
dB
dB
dBm
dBm
dB
µs
O
Attenuation Accuracy
1 dB Compression
3
Input IP3
1, 2
Return Loss
Switching Speed
Operation Frequency
EP
LA
Any Bit or Bit
Combination
Two-tone inputs
+18 dBm
50% control to 0.5 dB
of final value
R
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. See Max input rating in Table 3 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
Document No. 70-0159-06
│
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©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
E
DC - 2.2 GHz
DC - 2.2 GHz
1 MHz - 2.2 GHz
1 MHz - 2.2 GHz
DC - 2.2 GHz
PE4305
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 3. Insertion Loss
Figure 4. Attenuation at Major steps
0
20
-1
Normalized Attenuation (dB)
15
15.5 dB
Insertion Loss (dB)
-2
10
-3
insertion loss @ 25 C
insertion loss @ -40 C
insertion loss @ 85 C
-4
LE
H
PE
T
5
2 dB
1 dB
500
-5
0
500
1000
1500
2000
2500
0
3000
3500
4000
0
43
12
.5 dB
1000
1500
2000
2500
3000
Frequency (MHz)
1000
1500
2000
2500
3000
Frequency (MHz)
E
8 dB
4 dB
3500
4000
Frequency (MHz)
Figure 5. Input Return Loss at Major
Attenuation Steps
0
O
IT
W
3500
4000
Figure 6. Output Return Loss at Major
Attenuation Steps
0
-10
BS
C
8 dB
-10
-20
S11 (dB)
-20
S22 (dB)
O
-40
-50
0
500
1000
-30
E
2500
3000
15.5 dB
-30
15.5 dB
-40
EP
LA
1500
2000
-50
0
500
3500
4000
Frequency (MHz)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
R
Document No. 70-0159-06
│
UltraCMOS™ RFIC Solutions
PE4305
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 7. Attenuation Error Vs. Frequency
Figure 8. Attenuation Error Vs. Attenuation
Setting at 10 MHz and 510 MHz
0.6
0.2
0.4
0
-0.2
Error (dB)
Error (dB)
0
-0.4
15.5 dB
-0.6
-0.8
-1
0
500
1000
1500
2000
2500
LE
H
PE
T
-0.2
510 MHz @ 25 C
-0.4
10 MHz @ -40 C
510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
4
6
-0.6
3500
4000
0
2
8
0.6
0.4
0.2
Error (dB)
0
-0.2
-0.4
1510 MHz @ 25 C
1510 MHz @ -40 C
1510 MHz @ 85 C
2010 MHz @ 25 C
2010 MHz @ -40 C
2010 MHz @ 85 C
-0.6
14
16
0
2
4
6
8
43
12
10
12
Attenuation State (dB)
10
12
Attenuation State (dB)
E
10 MHz @ 25 C
14
16
14
16
0.2
3000
Frequency (MHz)
Figure 9. Attenuation Error Vs. Attenuation
Setting 1010 MHz and 1210 MHz
0.6
0.4
0.2
Error (dB)
0
-0.6
EP
LA
0
2
4
6
8
10
Attenuation State (dB)
O
-0.2
-0.4
Note: Positive attenuation error indicates higher attenuation than target value
R
BS
C
1010 MHz @ 25 C
1010 MHz @ -40 C
1010 MHz @ 85 C
1210 MHZ @ 25 C
1210 MHz @ -40 C
1210 MHz @ 85 C
E
12
W
Document No. 70-0159-06
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O
IT
Figure 10. Attenuation Error Vs. Attenuation
Setting at
1510
MHz and 2010 MHz
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4305
Product Specification
Typical Performance Data @ 25°C, V
DD
= 3.0 V
Figure 11. Attenuation Error vs. Attenuation
Setting at
2010 MHz and 2510 MHz
0.6
Figure 12. 1 dB Compression vs. Frequency
40
0.4
35
1 dB Compression (dBm)
0
2010 MHz @ 25 C
2510 MHz @ 25 C
2010 MHz @ -40 C
2510 MHz @ -40 C
2010 MHz @ 85 C
2510 MHz @ 85 C
30
-0.2
LE
H
PE
T
25
20
14
16
1000
1500
3000
E
43
12
2000
2500
Frequency (MHz)
0 dB
0.5 dB
1 dB
2 dB
3000
0.2
Error (dB)
-0.4
-0.6
0
2
4
6
8
10
12
Attenuation State (dB)
Figure 13. Input IP3 vs. Frequency
55
50
45
IP3 (dBm)
40
35
30
25
20
EP
LA
500
1000
1500
2000
Frequency (MHz)
O
R
Page 4 of 11
Note: Positive attenuation error indicates higher attenuation than target value
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
BS
C
0 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.5 dB
60
E
2500
W
Document No. 70-0159-06
│
UltraCMOS™ RFIC Solutions
O
IT
PE4305
Product Specification
Figure 14. Pin Configuration (Top View)
GND
C0.5
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
16
N/C
RF1
Data
Clock
LE
1
2
3
4
5
10
15
C8
RF2
P/S
Vss/GND
GND
T
ST
P
IN
V
ESD
20-lead
QFN
4x4 mm
Exposed Solder Pad
14
13
12
11
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LE
H
PE
T
Table 4. Operating Ranges
Parameter
Min
2.7
V
DD
Power Supply
Voltage
I
DD
Power Supply
Current
Digital Input High
0.7xV
DD
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
-40
V
DD
V
DD
PUP2
GND
N/C
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
43
12
Typ
3.0
E
1
85
6
7
8
9
Pin Name
N/C
RF1
Data
Clock
LE
V
DD
N/C
PUP2
V
DD
GND
GND
Description
Max
3.3
Units
V
µA
V
V
µA
dBm
°C
No connect. Can be connected to any
bias.
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Power supply pin.
Latch Enable input (Note 2).
100
0.3xV
DD
No connect. Can be connected to any
bias.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
O
IT
E
W
+24
BS
C
V
ss
/GND
P/S
C8
C4
C2
C1
Negative supply voltage or GND
connection(Note 3)
RF port (Note 1).
Parallel/Serial mode select.
RF2
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
GND
C0.5
Attenuation control bit, 0.5 dB.
GND
Ground for proper operation
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
Switching Frequency
The PE4305 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 kΩ resistor on the input to Pin 3 (see Figure 16)
will eliminate package resonance between the RF input
pin and the digital input. Specified attenuation error
versus frequency performance is dependent upon this
condition.
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Paddle
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and disable
internal negative voltage generator.
Document No. 70-0159-06
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R
4. Place a 10 kΩ resistor in series, as close to pin as possible to
avoid frequency resonance. See “Resistor on Pin 3” paragraph.
EP
LA
O
FPGA/CPLD
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