P RE L I M I NA R Y
LM3S628 Microcontroller
D A TA SH EET
DS -LM3S 628- 01
C opyr ight © 2006 Lumi nary Micro , Inc.
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2
Preliminary
October 8, 2006
LM3S628 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 15
About This Document..................................................................................................................... 16
Audience........................................................................................................................................................... 16
About This Manual............................................................................................................................................ 16
Related Documents .......................................................................................................................................... 16
Documentation Conventions............................................................................................................................. 16
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 19
Product Features ................................................................................................................................. 19
Target Applications .............................................................................................................................. 22
High-Level Block Diagram ................................................................................................................... 23
Functional Overview ............................................................................................................................ 24
ARM Cortex™-M3 ............................................................................................................................... 24
Motor Control Peripherals .................................................................................................................... 24
Analog Peripherals .............................................................................................................................. 24
Serial Communications Peripherals..................................................................................................... 25
System Peripherals.............................................................................................................................. 26
Memory Peripherals............................................................................................................................. 26
Additional Features .............................................................................................................................. 27
Hardware Details ................................................................................................................................. 28
System Block Diagram ........................................................................................................................ 29
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 30
Block Diagram ..................................................................................................................................... 31
Functional Description ......................................................................................................................... 31
Serial Wire and JTAG Debug .............................................................................................................. 31
Embedded Trace Macrocell (ETM) ...................................................................................................... 32
Trace Port Interface Unit (TPIU) .......................................................................................................... 32
ROM Table .......................................................................................................................................... 32
Memory Protection Unit (MPU) ............................................................................................................ 32
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 32
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 33
Interrupts ............................................................................................................................. 35
JTAG Interface .................................................................................................................... 38
Block Diagram ..................................................................................................................................... 39
Functional Description ......................................................................................................................... 39
JTAG Interface Pins............................................................................................................................. 40
JTAG TAP Controller ........................................................................................................................... 41
Shift Registers ..................................................................................................................................... 42
Operational Considerations ................................................................................................................. 42
Initialization and Configuration............................................................................................................. 43
Register Descriptions........................................................................................................................... 44
Instruction Register (IR) ....................................................................................................................... 44
Data Registers ..................................................................................................................................... 46
6.
6.1
6.1.1
System Control.................................................................................................................... 48
Functional Description ......................................................................................................................... 48
Device Identification............................................................................................................................. 48
October 8, 2006
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 48
Power Control ...................................................................................................................................... 51
Clock Control ....................................................................................................................................... 51
System Control .................................................................................................................................... 53
Initialization and Configuration............................................................................................................. 54
Register Map ....................................................................................................................................... 54
Register Descriptions........................................................................................................................... 55
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 88
Block Diagram ..................................................................................................................................... 88
Functional Description ......................................................................................................................... 88
SRAM Memory .................................................................................................................................... 88
Flash Memory ...................................................................................................................................... 89
Initialization and Configuration............................................................................................................. 90
Changing Flash Protection Bits ........................................................................................................... 90
Flash Programming ............................................................................................................................. 91
Register Map ....................................................................................................................................... 91
Register Descriptions........................................................................................................................... 92
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 102
Block Diagram ................................................................................................................................... 103
Functional Description ....................................................................................................................... 103
Data Register Operation .................................................................................................................... 104
Data Direction .................................................................................................................................... 105
Interrupt Operation............................................................................................................................. 105
Mode Control ..................................................................................................................................... 106
Pad Configuration .............................................................................................................................. 106
Identification....................................................................................................................................... 106
Initialization and Configuration........................................................................................................... 106
Register Map ..................................................................................................................................... 108
Register Descriptions......................................................................................................................... 109
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 140
Block Diagram ................................................................................................................................... 141
Functional Description ....................................................................................................................... 141
GPTM Reset Conditions .................................................................................................................... 141
32-Bit Timer Operating Modes........................................................................................................... 141
16-Bit Timer Operating Modes........................................................................................................... 143
Initialization and Configuration........................................................................................................... 147
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 147
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 148
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 148
16-Bit Input Edge Count Mode .......................................................................................................... 148
16-Bit Input Edge Timing Mode ......................................................................................................... 149
16-Bit PWM Mode.............................................................................................................................. 149
Register Map ..................................................................................................................................... 150
Register Descriptions......................................................................................................................... 151
10.
10.1
10.2
10.3
10.4
Watchdog Timer ................................................................................................................ 172
Block Diagram ................................................................................................................................... 172
Functional Description ....................................................................................................................... 173
Initialization and Configuration........................................................................................................... 173
Register Map ..................................................................................................................................... 173
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Preliminary
October 8, 2006
LM3S628 Data Sheet
10.5
Register Descriptions......................................................................................................................... 174
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 195
Block Diagram ................................................................................................................................... 195
Functional Description ....................................................................................................................... 196
Sample Sequencers .......................................................................................................................... 196
Module Control .................................................................................................................................. 197
Hardware Sample Averaging Circuit.................................................................................................. 197
Analog-to-Digital Converter ............................................................................................................... 197
Test Modes ........................................................................................................................................ 197
Internal Temperature Sensor ............................................................................................................. 198
Initialization and Configuration........................................................................................................... 198
Module Initialization ........................................................................................................................... 198
Sample Sequencer Configuration ...................................................................................................... 198
Register Map ..................................................................................................................................... 199
Register Descriptions......................................................................................................................... 200
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 225
Block Diagram ................................................................................................................................... 226
Functional Description ....................................................................................................................... 226
Transmit/Receive Logic ..................................................................................................................... 226
Baud-Rate Generation ....................................................................................................................... 227
Data Transmission ............................................................................................................................. 228
FIFO Operation .................................................................................................................................. 228
Interrupts............................................................................................................................................ 228
Loopback Operation .......................................................................................................................... 229
Initialization and Configuration........................................................................................................... 229
Register Map ..................................................................................................................................... 230
Register Descriptions......................................................................................................................... 231
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 261
Block Diagram ................................................................................................................................... 261
Functional Description ....................................................................................................................... 262
Bit Rate Generation ........................................................................................................................... 262
FIFO Operation .................................................................................................................................. 262
Interrupts............................................................................................................................................ 262
Frame Formats .................................................................................................................................. 263
Initialization and Configuration........................................................................................................... 270
Register Map ..................................................................................................................................... 271
Register Descriptions......................................................................................................................... 272
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
14.5
14.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 296
Block Diagram ................................................................................................................................... 296
Functional Description ....................................................................................................................... 296
I
2
C Bus Functional Overview ............................................................................................................. 297
Available Speed Modes ..................................................................................................................... 304
Initialization and Configuration........................................................................................................... 305
Register Map ..................................................................................................................................... 306
Register Descriptions (I2C Master).................................................................................................... 306
Register Descriptions (I2C Slave)...................................................................................................... 320
October 8, 2006
Preliminary
5
Embedded System
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