74LVQ573
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 5.8 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ573MTR
74LVQ573TTR
DESCRIPTION
The 74LVQ573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
Figure 1: Pin Connection And IEC Logic Symbols
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state. In order to enhance PC board
layout, the 74LVQ573 offers a pinout having inputs
and outputs on opposite side of the package.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2004
Rev. 5
1/13
74LVQ573
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
Parameter
Value
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
0 to 10
Unit
V
V
V
°C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
3.0
to
3.6
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
V
OL
Low Level Output
Voltage
I
O
=50
µA
3.0
3.6
3.6
3.6
3.6
I
O
=12 mA
I
O
=24 mA
I
I
I
OZ
I
CC
I
OLD
I
OHD
Input Leakage Current
High Impedance Output
Leakage Current
Quiescent Supply
Current
Dynamic Output Current
(note 1, 2)
V
I
= V
CC
or GND
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
±
0.1
±0.25
4
36
-25
0.002
0
0.1
0.36
T
A
= 25°C
Min.
2.0
0.8
2.9
2.58
2.99
2.9
2.48
2.2
0.1
0.44
0.55
±
1
±
2.5
40
25
-25
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
0.1
0.44
0.55
±
1
±
5.0
40
µA
µA
µA
mA
mA
V
V
Max.
-55 to 125°C Unit
Min.
2.0
0.8
Max.
V
V
V
IH
V
IL
V
OH
High Level Input Voltage
Low Level Input Voltage
High Level Output
Voltage
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/13
74LVQ573
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
C
L
= 50 pF
3.3
0.8
V
T
A
= 25°C
Min.
Typ.
0.5
-0.8
2
-0.6
Max.
0.8
V
V
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
T
A
= 25°C
Min.
Typ.
7.2
5.8
7.2
5.8
8.7
7.4
8.5
7.5
2.0
1.5
0.0
0.0
0.0
0.0
0.5
0.5
Max.
11.5
9.0
11.5
9.0
14.0
11.5
14.0
11.5
5.0
4.0
4.0
3.0
1.5
1.5
1.0
1.0
Value
-40 to 85°C
Min.
Max.
13.5
10.5
13.5
10.5
16.0
13.5
16.0
13.5
6.0
4.0
4.5
3.0
1.5
1.5
1.0
1.0
-55 to 125°C
Min.
Max.
15.5
12.0
15.5
12.0
18.5
15.5
18.5
15.5
6.0
4.0
4.5
3.0
1.5
1.5
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time LE to Q
t
PLH
t
PHL
Propagation Delay
Time D to Q
t
PLZ
t
PHZ
t
PZL
t
PZH
t
W
t
sL
t
sH
t
hL
t
hH
t
OSLH
t
OSHL
Output Disable
Time
Output Enable
Time
LE Pulse Width
HIGH
Setup Time D to LE
HIGH or LOW
Hold Time D to LE,
HIGH or LOW
Output To Output
Skew Time
(note1, 2)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
4/13
74LVQ573
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
3.3
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
8
10
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
pF
Unit
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per latch)
Figure 4: Test Circuit
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
SWITCH
Open
2V
CC
Open
5/13
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