74LVX574
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 125MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LVX574 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE). On
the positive transition of the clock, the Q outputs
will be set to the logic state that were setup at the
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
e
uc
d
s)
t(
D inputs. While the (OE) input is low, the 8 outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state. The output control does not
affect the internal operation of flip flops; that is, the
old data can be retained or the new data can be
entered even while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
le
ro
P
uc
d
s)
t(
T&R
74LVX574MTR
74LVX574TTR
August 2004
Rev. 3
1/13
74LVX574
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 2) (V
CC
= 3V)
Parameter
Value
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
IH
V
IL
V
OH
O
et
l
so
b
Low Level Input
Voltage
High Level Input
Voltage
ro
P
e
V
CC
(V)
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
uc
d
s)
t(
O
-
Min.
1.5
2.0
2.4
s
b
te
le
o
Value
2 to 3.6
0 to 5.5
ro
P
uc
d
s)
t(
Unit
V
V
V
°C
ns/V
0 to V
CC
0 to 100
-55 to 125
T
A
= 25°C
Typ.
Max.
-40 to 85°C
Min.
1.5
2.0
2.4
0.5
0.8
0.8
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.36
0.1
0.1
0.44
±
2.5
±
1
40
Max.
-55 to 125°C Unit
Min.
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.4
0.1
0.1
0.55
±
2.5
±
1
40
µA
µA
µA
V
V
Max.
V
V
High Level Output
Voltage
I
O
=-50
µA
I
O
=-50
µA
I
O
=-4 mA
I
O
=50
µA
I
O
=50
µA
I
O
=4 mA
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
V
I
= 5V or GND
V
I
= V
CC
or GND
1.9
2.9
2.58
2.0
3.0
0.0
0.0
V
OL
Low Level Output
Voltage
I
OZ
I
I
I
CC
High Impedance
Output Leakage
Current
Input Leakage Current
Quiescent Supply
Current
3.6
3.6
3.6
±0.25
±
0.1
4
3/13
74LVX574
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
T
A
= 25°C
Min.
Typ.
0.3
-0.8
C
L
= 50 pF
2.0
-0.3
V
Max.
0.8
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
3.3
3.3
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
2.7
3.3
(*)
2.7
C
L
(pF)
15
50
15
50
15
50
T
A
= 25°C
Min.
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
t
W
t
S
t
h
f
MAX
O
et
l
so
b
Output Disable
Time
od
r
P
e
3.3
(*)
15
50
50
50
50
50
50
50
50
15
50
15
50
50
50
50
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
(*)
uc
)-
(s
t
b
O
Typ.
9.2
11.5
8.5
11.0
9.8
11.4
8.2
10.7
12.1
11.0
6.5
5.0
5.0
3.5
1.5
1.5
so
Max.
14.5
18.0
13.2
16.7
15.0
18.5
12.8
16.3
19.1
15.0
te
le
Value
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ro
P
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
uc
d
Max.
17.5
21.0
15.5
19.0
18.5
22.0
15.0
18.5
22.0
17.0
7.5
5.0
5.0
3.5
1.5
1.5
s)
t(
-40 to 85°C
Max.
17.5
21.0
15.5
19.0
18.5
22.0
15.0
18.5
22.0
17.0
7.5
5.0
5.0
3.5
1.5
1.5
50
40
65
45
-55 to 125°C
Unit
ns
ns
ns
ns
ns
ns
CK pulse Width,
HIGH
Setup Time D to CK
HIGH or LOW
Hold Time D to CK
HIGH or LOW
Maximum Clock
Frequency
60
45
80
50
115
60
125
75
0.5
0.5
1.0
1.0
48
40
60
40
1.5
1.5
1.5
1.5
ns
MHz
t
OSLH
t
OSHL
Output to Output
Skew Time (note
1,2)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
4/13
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