EN25F40
EN25F40
4 Mbit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
•
Single power supply operation
- Full voltage range: 2.7-3.6 volt
•
4 Mbit Serial Flash
- 4 M-bit/512 K-byte/2048 pages
- 256 bytes per programmable page
•
High performance
- 100MHz clock rate
•
Low power consumption
- 5 mA typical active current
- 1
μA
typical power down current
•
-
-
-
Uniform Sector Architecture:
128 sectors of 4-Kbyte
8 blocks of 64-Kbyte
Any sector or block can be
erased individually
•
-
-
-
-
High performance program/erase speed
Page program time: 1.5ms typical
Sector erase time: 150ms typical
Block erase time 800ms typical
Chip erase time: 5 Seconds typical
•
Lockable 256 byte OTP security sector
•
Minimum 100K endurance cycle
•
Package Options
-
-
-
-
-
8 pins SOP 150mil body width
8 pins SOP 200mil body width
8 contact VDFN
8 pins PDIP
All Pb-free packages are RoHS compliant
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25F40 is a 4M-bit (512K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25F40 is designed to allow either single Sector at a time or full chip erase operation. The
EN25F40 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/11/23
EN25F40
Figure.1 CONNECTION DIAGRAMS
8 - LEAD SOP / PDIP
8 - CONTACT VDFN
Figure 2. BLOCK DIAGRAM
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/11/23
EN25F40
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device
is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the
devices power consumption will be at standby levels unless an internal erase, program or status
register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/11/23
EN25F40
MEMORY ORGANIZATION
The memory is organized as:
524,288 bytes
Uniform Sector Architecture
8 blocks of 64-Kbyte
128 sectors of 4-Kbyte
2048 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
7
Sector
127
….
112
111
….
6
96
95
….
5
80
79
….
4
64
63
….
3
48
47
….
2
32
31
….
1
16
15
….
4
3
2
1
0
Address range
07F000h
….
070000h
06F000h
….
060000h
05F000h
….
050000h
04F000h
….
040000h
03F000h
….
030000h
02F000h
….
020000h
01F000h
….
010000h
00F000h
….
004000h
003000h
002000h
001000h
000000h
07FFFFh
070FFFh
06FFFFh
060FFFh
05FFFFh
050FFFh
04FFFFh
040FFFh
03FFFFh
030FFFh
02FFFFh
020FFFh
01FFFFh
010FFFh
00FFFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
….
….
….
….
….
….
….
….
0
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/11/23
EN25F40
OPERATING FEATURES
SPI Modes
The EN25F40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus
operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus
master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is
sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge
of CLK.
Figure 3. SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the
internal Program cycle (of duration t
PP
).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on
the same page of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied,
the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a
time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE)
instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an
internal Erase cycle (of duration t
SE
t
BE
or t
CE
). The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE
or CE ) can be achieved by not waiting for the worst case delay (t
W
, t
PP
, t
SE
, t
BE
or t
CE
). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all
internal cycles have completed (Program, Erase, Write Status Register). The device then goes into
the Stand-by Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to I
CC2
. The device re-
mains in this mode until another specific instruction (the Release from Deep Power-down Mode and
Read Device ID (RDI) instruction) is executed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/11/23
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