74V1T02
SINGLE 2-INPUT NOR GATE
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.1ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1µA(MAX.) at T
A
=25°C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1T02STR
74V1T02CTR
DESCRIPTION
The 74V1T02 is an advanced high-speed CMOS
SINGLE 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2004
1/9
74V1T02
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N°
1
2
4
3
5
SYMBOL
1A
1B
1Y
GND
V
CC
NAME AND FUNCTION
Data Input
Data Input
Data Output
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
A
L
L
H
H
B
L
H
L
H
Y
H
L
L
L
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
50
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 5.0
±
0.5V)
Parameter
Value
4.5 to 5.5
0 to 5.5
0 to V
CC
-55 to 125
0 to 20
Unit
V
V
V
°C
ns/V
1) V
IN
from 0.8V to 2V
2/9
74V1T02
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
4.5 to
5.5
4.5 to
5.5
4.5
4.5
4.5
4.5
0 to
5.5
5.5
5.5
I
O
=-50
µA
I
O
=-8 mA
I
O
=50
µA
I
O
=8 mA
V
I
= 5.5V or GND
V
I
= V
CC
or GND
One Input at 3.4V,
other input at V
CC
or GND
T
A
= 25°C
Min.
2
0.8
4.4
3.94
0.0
0.1
0.36
±
0.1
1
1.35
4.5
4.4
3.8
0.1
0.44
±
1.0
10
1.5
Typ.
Max.
Value
-40 to 85°C
Min.
2
0.8
4.4
3.7
0.1
0.55
±
1.0
20
1.5
µA
µA
mA
V
Max.
-55 to 125°C
Min.
2
0.8
Max.
V
V
V
Unit
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
+I
CC
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Additional Worst
Case Supply
Current
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
5.0 (*)
5.0 (*)
C
L
(pF)
15
50
T
A
= 25°C
Min.
Typ.
4.5
5.1
Max.
6.5
7.5
Value
-40 to 85°C
Min.
1.0
1.0
Max.
7.5
8.5
-55 to 125°C
Min.
1.0
1.0
Max.
8.5
9.5
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
(*) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
T
A
= 25°C
Min.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
Typ.
4
10
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
3/9
74V1T02
TEST CIRCUIT
C
L
= 15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAY
(f=1MHz; 50% duty cycle)
4/9
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
