74VHC240
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (INVERTED)
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 240
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC240MTR
74VHC240TTR
DESCRIPTION
The 74VHC240 is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
G output enable governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 5
1/12
74VHC240
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 4, 6, 8
9, 7, 5, 3
11, 13, 15,
17
18, 16, 14,
12
19
10
20
SYMBOL
1G
1A1 to 1A4
2Y1 to 2Y4
2A1 to 2A4
1Y1 to 1Y4
2G
GND
V
CC
NAME AND FUNCTION
Output Enable Input
Data Inputs
Data Outputs
Data Inputs
Data Outputs
Output Enable Input
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
G
L
L
H
X : Don‘t Care
Z : High Impedance
OUTPUT
An
L
H
X
Yn
H
L
Z
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
75
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
Value
2 to 5.5
0 to 5.5
0 to V
CC
-55 to 125
0 to 100
0 to 20
Unit
V
V
V
°C
ns/V
1) V
IN
from 30% to 70% of V
CC
2/12
74VHC240
Table 7: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PLZ
t
PHZ
t
OSLH
t
OSHL
Output Disable
Time
Output to Output
Skew time (note 1)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
C
L
(pF)
15
50
15
50
15
50
15
50
50
50
50
50
R
L
= 1K
Ω
R
L
= 1K
Ω
R
L
= 1K
Ω
R
L
= 1K
Ω
R
L
= 1K
Ω
R
L
= 1K
Ω
T
A
= 25°C
Min.
Typ.
5.3
7.8
3.6
5.1
6.6
9.1
4.7
6.2
10.3
6.7
Max.
7.5
11.0
5.5
7.5
10.6
14.1
7.3
9.3
14.0
9.2
1.5
1.0
Value
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
9.0
12.5
6.5
8.5
12.5
16.0
8.5
10.5
16.0
10.5
1.5
1.0
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
9.0
12.5
6.5
8.5
12.5
16.0
8.5
10.5
16.0
10.5
1.5
1.0
ns
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Table 8: Capacitive Characteristics
Test Condition
Symbol
Parameter
T
A
= 25°C
Min.
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
Typ.
6
8
17
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
pF
Unit
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per circuit)
4/12
74VHC240
Table 9: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
T
A
= 25°C
Min.
Typ.
0.6
-0.9
C
L
= 50 pF
3.5
-0.6
Max.
0.9
V
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
5.0
V
5.0
1.5
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Figure 3: Test Circuit
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
=15/ 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 1KΩ or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
SWITCH
Open
V
CC
GND
5/12
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