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74VHC27_04

Description
TRIPLE 3-INPUT NOR GATE
File Size135KB,10 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
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74VHC27_04 Overview

TRIPLE 3-INPUT NOR GATE

74VHC27
TRIPLE 3-INPUT NOR GATE
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.1 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 27
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74VHC27 is an advanced high-speed CMOS
TRIPLE 3-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Figure 1: Pin Connection And IEC Logic Symbols
O
et
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ro
P
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uc
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t(
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
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ro
P
uc
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t(
T&R
74VHC27MTR
74VHC27TTR
November 2004
Rev. 4
1/10

74VHC27_04 Related Products

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Description TRIPLE 3-INPUT NOR GATE TRIPLE 3-INPUT NOR GATE

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