EEWORLDEEWORLDEEWORLD

Part Number

Search

531RB929M000DGR

Description
LVPECL Output Clock Oscillator, 929MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531RB929M000DGR Overview

LVPECL Output Clock Oscillator, 929MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531RB929M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency929 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Wireless chip faster than 5G is born
Even before 5G becomes popular, researchers are already moving toward 6G. The next generation of mobile communications may require Tbps speeds, which far exceeds the theoretical capacity of 10 Gbps un...
ohahaha RF/Wirelessly
What are the functions of these two diodes and which models should be selected?
This circuit converts the three-wire signal of the synchro into a 2V sin and cos signal acceptable to AD2S83. The upper one is the reference voltage input. What is the role of the diode here? Should t...
我爱一帆 Analog electronics
Error LNK1123 when using platform builder sysgen
Hello everyone, I used platformbuilder to compile the operating system given by the manufacturer and it was successful, but it only had an arm cpu. I added the emulator's cpu and switched to sysgen, b...
yattai Embedded System
Grid automation: a bright future for the rapid development of the power grid
Electric vehicles can power your home with a bidirectional charger. Smart meters can help you lower your water bill. Wireless sensors can detect a faulty transformer before the lights go out. The futu...
alan000345 TI Technology Forum
Can a 5V crystal oscillator be connected in series with a resistor for use with a 3.3V CPLD?
[i=s] This post was last edited by tcxz111 on 2016-12-13 09:36 [/i] The 5V crystal oscillator is used for the CAN controller. Due to timing reasons, it is hoped that the CPLD and the CAN controller ca...
tcxz111 FPGA/CPLD
An even number of NOT gates with a short delay prevents optimization issues
I want to ask, if I write a VHDL program that uses an even number of NOT gates to perform a short delay and then output, what is the statement that can be added to the synthesis constraint comment par...
eeleader FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2060  2363  1146  185  2305  42  48  24  4  47 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号