Power dissipation is for the AD7626 only. In self-clocked interface, 9mW is dissipated in the 100 ohm terminator. In echoed-clock interface, 18mW is dissipated in (2)
100 ohm terminators.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.3V to 2.7 V; V
REF
= 4.096 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
Time between conversion
Acquisition time
CNV high time
CNV to D (MSB) delay
CNV to last CLK (LSB) delay
CLK period
CLK frequency
CLK to DCO delay (echoed-clock mode)
DCO to D delay (echoed-clock mode)
CLK to D delay
Symbol
t
CYC
t
ACQ
t
CNVH
t
MSB
t
CLKL
t
CLK
f
CLK
t
DCO
t
D
t
CLKD
Min
100
40
10
Typ
Max
10000
40
166
120
4
250
4
0
4
400
7
1
7
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
TBD
0
-1
0
Rev. PrB | Page 4 of 11
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Analog Inputs/Outputs
CAP1, REFIN
IN+, IN-, REF, REF/2,
CAP2
Digital Inputs/Outputs
Supply Voltage
VDD1
VDD2, VIO
With
Respect to
GND
GND
GND
GND
GND
Rating
AD7625
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
-0.3V to 2.7V
-0.3V to 6V
-0.3V to 2.7V
-0.3V to 6V
-0.3V to 2.7V
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
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FPGA/CPLD
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