Bias Voltage for U Phase IC and Low Side FRFET Driving
Signal Input for U Phase High-side
Signal Input for U Phase Low-side
Bias Voltage Ground for U Phase High Side FRFET Driving
Bias Voltage for V Phase High Side FRFET Driving
Bias Voltage for V Phase IC and Low Side FRFET Driving
Signal Input for V Phase High-side
Signal Input for V Phase Low-side
Bias Voltage Ground for V Phase High Side FRFET Driving
Bias Voltage for W Phase High Side FRFET Driving
Bias Voltage for W Phase IC and Low Side FRFET Driving
Signal Input for W Phase High-side
Signal Input for W Phase Low-side
Bias Voltage Ground for W Phase High Side FRFET Driving
Positive DC–Link Input
Output for U Phase
Negative DC–Link Input for U Phase
Negative DC–Link Input for V Phase
Output for V Phase
Negative DC–Link Input for W Phase
Output for W Phase
(1) COM
(2) V
B(U)
(3) V
CC(U)
(4) IN
(UH)
(5) IN
(UL)
(6) V
S(U)
(7) V
B(V)
(8) V
CC(V)
(9) IN
(VH)
(10) IN
(VL)
(11) V
S(V)
(12) V
B(W)
(13) V
CC(W)
(14) IN
(WH)
(15) IN
(WL)
(16) V
S(W)
Note:
Source terminal of each MOSFET is not connected to supply ground or bias voltage ground inside SPM
®
. External connections should be made as indicated in Figure 2 and 5.
(17) P
VCC
HIN
LIN
COM
VB
HO
VS
LO
(19) N
U
VCC
HIN
LIN
COM
VB
HO
VS
LO
(21) V
(20) N
V
(18) U
VCC
HIN
LIN
COM
VB
HO
VS
LO
(22) N
W
(23) W
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
2
FSB50325 Rev. C
www.fairchildsemi.com
FSB50325 Smart Power Module (SPM®)
Electrical Characteristics
(T
J
= 25°C, V
CC
=V
BS
=15V Unless Otherwise Specified)
Inverter Part
(Each FRFET Unless Otherwise Specified)
Symbol
BV
DSS
ΔBV
DSS
/
ΔT
J
I
DSS
R
DS(on)
V
SD
t
ON
t
OFF
t
rr
E
ON
E
OFF
RBSOA
(Note 3)
V = 200V, V
CC
= V
BS
= 15V, I
D
= I
DP
, R
EH
= 0Ω
Reverse-bias Safe Oper-
PN
V
DS
=BV
DSS
, T
J
= 150°C
ating Area
High- and low-side FRFET switching (Note 4)
Switching Times
Parameter
Conditions
Min Typ Max Units
250
-
-
-
-
-
-
-
-
-
-
0.31
-
1.4
-
1076
660
108
47
3.1
-
-
250
1.8
1.2
-
-
-
-
-
V
V
μA
Ω
V
ns
ns
ns
μJ
μJ
Drain-Source Breakdown
V
IN
= 0V, I
D
= 250μA (Note 2)
Voltage
Breakdown Voltage Tem-
I
D
= 250μA, Referenced to 25°C
perature Coefficient
Zero Gate Voltage
Drain Current
Static Drain-Source
On-Resistance
Drain-Source Diode
Forward Voltage
V
IN
= 0V, V
DS
= 250V
V
CC
= V
BS
= 15V, V
IN
= 5V, I
D
= 1.0A
V
CC
= V
BS
= 15V, V
IN
= 0V, I
D
= -1.0A
V
PN
= 150V, V
CC
= V
BS
= 15V, I
D
= 1.0A
V
IN
= 0V
↔
5V, R
EH
= 0Ω
Inductive load L=3mH
High- and low-side FRFET switching
Full Square
Control Part
(Each HVIC Unless Otherwise Specified)
Symbol
I
QCC
I
QBS
UV
CCD
UV
CCR
UV
BSD
UV
BSR
V
IH
V
IL
I
IH
I
IL
Note:
1. For the measurement point of case temperature T
C
, please refer to Figure 3 in page 4.
2. BV
DSS
is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM
®
. V
PN
should be sufficiently less than this value considering the
effect of the stray inductance so that V
DS
should not exceed BV
DSS
in any case.
3. t
ON
and t
OFF
include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test cir-
cuit that is same as the switching test circuit.
Parameter
Quiescent V
CC
Current
Quiescent V
BS
Current
Low-side Undervoltage
Protection (Figure 6)
High-side Undervoltage
Protection (Figure 7)
ON Threshold Voltage
OFF Threshold Voltage
Input Bias Current
V
CC
=15V, V
IN
=0V
V
BS
=15V, V
IN
=0V
Conditions
Applied between V
CC
and COM
Applied between V
B
and V
S
Min Typ Max Units
-
-
7.4
8.0
7.4
8.0
3.0
-
-
-
-
-
8.0
8.9
8.0
8.9
-
-
10
-
160
100
9.4
9.8
9.4
9.8
-
0.8
20
2
μA
μA
V
V
V
V
V
V
μA
μA
V
CC
Undervoltage Protection Detection Level
V
CC
Undervoltage Protection Reset Level
V
BS
Undervoltage Protection Detection Level
V
BS
Undervoltage Protection Reset Level
Logic High Level
Logic Low Level
V
IN
= 5V
V
IN
= 0V
Applied between IN and COM
Applied between IN and COM
Package Marking & Ordering Information
Device Marking
FSB50325
Device
FSB50325
Package
SPM23AA
Reel Size
_
Tape Width
_
Quantity
15
3
FSB50325 Rev. C
www.fairchildsemi.com
FSB50325 Smart Power Module (SPM®)
Recommended Operating Conditions
Symbol
V
PN
V
CC
V
BS
V
IN(ON)
V
IN(OFF)
t
dead
f
PWM
T
C
Parameter
Supply Voltage
Control Supply Voltage
High-side Bias Voltage
Input ON Threshold Voltage
Input OFF Threshold Voltage
Conditions
Applied between P and N
Applied between V
CC
and COM
Applied between V
B
and V
S
Applied between IN and COM
Value
Min.
-
13.5
13.5
3.0
0
1.0
-
-20
-
15
Typ.
150
15
15
Max.
200
16.5
16.5
V
CC
0.6
-
-
125
Units
V
V
V
V
V
μs
kHz
°C
Blanking Time for Preventing
V
CC
=V
BS
=13.5 ~ 16.5V, T
J
≤
150°C
Arm-short
PWM Switching Frequency
Case Temperature
T
J
≤
150°C
T
J
≤
150°C
These values depend on PWM
control algorithm
15-V Line
R
1
D
1
VCC
HIN
LIN
C
5
COM
VB
HO
VS
LO
N
C
2
C
1
One-Leg Diagram of SPM
* Example of bootstrap paramters:
C
1
= C
2
= 1μF ceramic capacitor,
R
1
= 56Ω, R
2
= 20Ω
R
3
R
2
P
V
DC
HIN
0
LIN
0
1
0
1
Open
Output
Z
0
V
DC
Forbidden
Z
Note
Both FRFET Off
Low-side FRFET On
High-side FRFET On
Shoot-through
Same as (0, 0)
R
5
Inverter
Output
C
3
0
1
1
Open
Micom
10μF
Note:
(1) It is recommended the bootstrap diode D
1
to have soft and fast recovery characteristics with 600-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
(3) RC coupling(R
5
and C
5
) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM
®
is compatible with
standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C
1
, C
2
and C
3
should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50 mm
3.80 mm
MOSFET
Note:
Case Temperature (T
C
)
Detecting Point
Attach the thermocouple on top of the heatsink-side of SPM
®
(between SPM
®
and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
4
FSB50325 Rev. C
www.fairchildsemi.com
FSB50325 Smart Power Module (SPM®)
V
IN
I
rr
V
DS
100% of I
D
120% of I
D
V
IN
I
D
10% of I
D
I
D
V
DS
t
ON
t
rr
t
OFF
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
R
EH
V
CC
R
BS
VCC
HIN
LIN
COM
VB
HO
VS
LO
+
V
DS
-
L
V
DC
I
D
C
BS
One-leg Diagram of SPM
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
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