White Electronic Designs
PCMCIA Flash Memory Card
FLA Series
PCMCIA Flash Memory Card
1 MEGABYTE through 40 MEGABYTE (Intel/Sharp based)
FEATURES
Low cost High Density Linear Flash Card
Supports 5V only systems or 5V systems with
12V VPP
Based on Intel/Sharp FlashFile Components
Fast Read Performance
- 150ns or 200ns Maximum Access Time
x8 / x16 Data Interface
High Performance Random Writes
- 8µs Typical Word Write Time
Automated Write and Erase Algorithms
- Command User Interface
100,000 Erase Cycles per Block
64K word symmetrical Block Architecture
PC Card Standard Type I Form Factor
ARCHITECTURE OVERVIEW
WEDC’s FLA series is designed to support from 2 to 20,
4Mb, 8Mb or 16Mb components, providing a wide range
of density options. Cards are based on the 28F008SA
(8Mb) for 12V VPP applications or on the 28F004S5
(4Mb), 28F008S5 (8Mb) and 28F016S5 (16Mb) devices
for 5V only applications. Devices codes for the 28F004S5,
28F008SA, 28F008S5 and the 28F016S5 are: A7H,
A2H, A6H and AAh respectively. Systems should be
able to recognize all four codes. Cards utilizing the 8Mb
components provide densities ranging from 2MB to 20MB
in 2MB increments, cards utilizing 16Mb components
provide densities ranging from 4MB to 40MB in 4MB
increments. 4 Mbit memory devices are used only for
smallest capacity cards (1MB).
In support of the PC Card 95 standard for word wide
access devices are paired. Therefore, the Flash array is
structured in 64K word (128kBytes) blocks. Write, read
and block erase operations can be performed as either
a word or byte wide operation . By multiplexing A
0
, CE
1#
and CE
2
,# 8-bit hosts can access all data on data lines
DQ
0
-DQ
7
.
The
FLA21-FLA36
series also supports the following
PCMCIA compatible register functions: Soft Reset via the
Configuration Option Register, Power Down (sleep mode)
via the Configuration and Status Register and monitoring
of Ready/Busy, Soft Reset and Power Down via the Card
Status Register (cards without attribute memory and
versions
FLA51 - FLA66
do not have registers).
The FLA series cards conform with the PC Card Standard
(PCMCIA) and JEIDA, providing electrical and physical
compatibility. The PC Card form factor offers an industry
standard pinout and mechanical outline, allowing density
upgrades without system design changes.
WEDC’s standard cards are shipped with WEDC’s Logo.
Cards are also available with blank housings (no Logo).
The blank housings are available in both a recessed
(for label) and flat housing. Please contact WEDC
sales representative for further information on Custom
artwork.
GENERAL DESCRIPTION
WEDC’s FLA Series Flash memory cards offer high density
linear Flash solid state storage solutions for code and data
storage, high performance disk emulation and execute
in place (XIP) applications in mobile PC and dedicated
(embedded) equipment.
FLA series cards conform to PCMCIA international
standard.
The card’s control logic provides the system interface
and controls the internal Flash memories. Card can be
read/written in byte-wide or word-wide mode which allows
for flexible integration into various systems. Combined
with file management software, such as Flash Translation
Layer (FTL), FLA Flash cards provide removable high-
performance disk emulation.
The FLA series offers low power modes controlled by
registers. Standard cards contain separate 2kB EEPROM
memory for Card Information Structure (CIS) which can be
used for easy identification of card characteristics.
The WEDC FLA series is based on Intel/Sharp Flash
memories.
Note: Standard options include attribute memory. Cards without attribute memory are
available. Cards are also available with or without a hardware write protect switch.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2007
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
REGISTERS IN ATTRIBUTE MEMORY SPACE*
ADDRESS
4100h
4002h
REGISTER NAME
Status Register
Config. and Status Register
PCMCIA Flash Memory Card
FLA Series
CSR
CONFIGURATION STATUS REGISTER: ADRS =
4002H WRITE ONLY
Not Supported
D7
D6
D5
D4
D3
PDwn
D2
Not Supported
D1
D0
4000h
Configuration Option Register
*Cards without Att. Mem and FLA51- FLA66 do not have
registers
D2
Power Down, active High
1 = Place all memory devices in power down mode
COR
CONFIGURATION OPTION REGISTER: ADRS =
4000H WRITE ONLY
SRES
D7
0 = Normal Operation
default = 0
Power On
LREQ
D6
D5
D4
Configuration Index
D3
D2
D1
D0
D7
Soft Reset, active High
1 = Reset State
0 = End Reset State
SR
STATUS REGISTER: ADRS = 4100H
READ ONLY
Not Supported
D7
D6
SReset
D5
D4
PDwn
D3
Not Supported
D2
D1
R/BSY
D0
D5
Represents the state of SRESET bit in COR (4000h)
1 = Reset
0 = Normal Operation
Power On default
D5 = 0
D6
D5-D0
Level Req (not supported)
Configuration index (not supported)
D3
(4002h)
Represents the state of Power Down bit (D2) in CSR
1 = Power Down
D0
Reflects the card's Ready/Busy signal (pin 16) driven
by
memory components Ready/
Busy outputs. This bit allows
software polling of the
card's Ready/Busy status.
1 = Ready
MECHANICAL
Interconnect area
1.6mm + 0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
1.0mm + 0.05
(0.039”)
Substrate area
54.0mm + 0.10
(2.126”)
1.0mm + 0.05
(0.039”)
10.0mm MIN
(0.400”)
85.6mm + 0.20
(3.370”)
3.3mm + T1 (0.130”)
T1=0.10mm unterconnect area
T1=0.20mm substrate area
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2007
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PCMCIA Flash Memory Card
FLA Series
CARD SIGNAL DESCRIPTION
Symbol
A0 - A25
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/
BSY#(*)
CD1#, CD2#
WP
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0, CE1#
and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7.
OUTPUT ENABLE: Active low signal gating read data from the memory card.
WRITE ENABLE: Active low signal gating write data to the memory card.
READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that
the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy with
internally timed erase or write activities.
CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the card.
The host shall monitor these signals to detect card insertion (pulled-up on host side).
WRITE PROTECT: Write protect reflects the status of the Write Protect switch on the memory card. WP set to high =
write protected, providing internal hardware write lockout to the Flash array.If card does not include optional write protect
switch, this signal will be pulled low internally indicating write protect = “off”.
PROGRAM/ERASE POWER SUPPLY: Provides programming voltages for card (12V). Not connected for 5V only card.
CARD POWER SUPPLY: (5.0V).
CARD GROUND
ATTRIBUTE MEMORY SELECT : Active low signal, enables access to Attribute Memory Plane, occupied by Card
Information Structure and Card Registers.
RESET: Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down signal for the
memory array.
WAIT: This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE: Notifies the host socket of the card’s V
CC
requirements. VS1 and VS2 are open to indicate a 5V card .
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating
OUTPUT
OUTPUT
V
PP
1, V
PP
2
V
CC
GND
REG#
RST(*)
WAIT#(*)
BVD1, BVD2
VS1, VS2
RFU
NC
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
(*) Signals not supported by FLA51-66 (N.C)
FUNCTIONAL TRUTH TABLE
READ function
Function Mode
CE
2#
CE
1#
A
0
OE#
WE#
REG#
Common Memory
D
15
-D
8
D
7
-D
0
REG#
Attribute Memory
D
15
-D
8
D
7
-D
0
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
H
H
H
L
L
H
H
H
L
L
H
L
L
L
H
H
L
L
L
H
X
L
H
X
X
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
X
X
X
Odd-Byte
Odd-Byte
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
X
Even-Byte
Odd-Byte
Even-Byte
X
X
L
L
L
L
X
L
L
L
L
High-Z
High-Z
High-Z
Not Valid
Not Valid
X
X
X
X
X
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
X
Even-Byte
X
Even-Byte
X
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2007
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
