Freescale Semiconductor
Advance Information
Document Number: MC33790
Rev 11.0, 3/2008
Two-Channel Distributed
System Interface (DSI) Physical
Interface Device
The 33790 is a dual channel physical layer interface IC for the
Distributed System Interface (DSI) bus. It is designed to meet
automotive requirements. It can also be used in non automotive
applications. It supports bidirectional communication between slave
and master ICs. Some slave devices derive a regulated 5.0 V from
the bus, which can be used to power sensors, thereby eliminating the
need for additional circuitry and wiring.
Features
•
•
•
•
•
•
•
•
•
•
Two Independent DSI Compatible Buses
Pinout Matched to MC68HC55 (SPI to DSI Logic)
Wave-Shaped Bus Output Voltage
Independent Thermal Shutdown and Current Limit
Return Signalling Current Detection
Internal Logic Input Pull ups and Pull downs
On-Board Charge Pump
2.0 kV ESD Capability
Communications Rate Up to 150 kbps
Pb-Free Packaging Designated by Suffix Code EG
Device
MC33790DW / R2
MCZ33790EG / R2
33790
DISTRIBUTED SYSTEM INTERFACE (DSI)
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
ORDERING INFORMATION
Temperature
Range (T
A
)
-40°C to 85°C
Package
16 SOICW
MC68HC55
DSI0F
DSI0S
Protocol
Converter
DSI0R
DSI1F
DSI1S
DSI1R
CPCAP
33790
VDD
GND
DSI0O
VSUP
DSI1O
GND
+5.0 V
+25 V
MCU
DSI
SLAVE
DEVICE
33793
BUS_IN
BUS_OUT
33793
BUS_IN
BUS_OUT
33793
Figure 1. 33790 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD (+5.0 V)
CPCAP
VSUP (IDLE Level)
+
Internal
Bias
Charge
Pump
Bus Supply
Voltage
DSI0F
DSI0S
Wave-
Shaper
Transmitter
Driver
Bus Current
Sense
DSI0O
DSI Bus
DSI0R
GND
+
DSI1F
DSI1S
Wave-
Shaper
Transmitter
Driver
Bus Current
Sense
DSI1O
DSI Bus
DSI1R
Figure 2. 33790 Simplified Internal Block Diagram
33790
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
CPCAP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
GND
DSI0O
VSUP
DSI10
GND
NC
NC
Figure 3. 33790 Pin Connections
Table 1. 33790 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 8.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
CPCAP
NC
NC
GND
DSI1O
VSUP
DSI0O
GND
VDD
Definition
This logic input controls the frame output for DSI channel 0 in accordance with
Table 5,
page
8.
This logic input controls the signalling output for DSI channel 0 in accordance with
Table 5,
page
8.
This logic output provides the return data for DSI channel 0 in accordance with
Table 5,
page
8.
This logic input controls the frame output for DSI channel 1 in accordance with
Table 5,
page
8.
This logic input controls the signalling output for DSI channel 1 in accordance with
Table 5,
page
8.
This logic output provides the return data for DSI channel 1 in accordance with
Table 5,
page
8.
Unused.
Used to store and filter charge pump output.
Unused.
Unused.
Circuit and bus ground return.
DSI bus 1 input / output.
Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus.
DSI bus 0 input / output.
Circuit and bus ground return.
5.0 V logic supply input.
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Supply Voltage
Continuous
Load Dump - t < 300 ms
Maximum Voltage on Input / Output Pins
V
SUP
V
SUP
(
t
)
V
DD
DSIxS, DSIxF
(1)
DSIxO
(1)
Storage Temperature
Operating Ambient Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow
(2)
,
(3)
Continuous Current per Pin
T
STG
T
A
T
J
T
PPRT
V
DD
DSIxR
V
SUP
Thermal Resistance Junction to Ambient
Thermal Shutdown
ESD Voltage (All Pins)
(4)
Human Body Model
Machine Model
V
ESD1
V
ESD2
±
2000
±
200
R
θ
JA
T
SD
- 0.5 to 25
40
- 0.3 to 5.5
- 0.3 to V
DD
+ 0.3
- 0.3 to V
SUP
+ 0.3
- 55 to 150
-40 to 85
- 40 to 150
Note 3
0 to 10
- 2.5 to 5.0
500
45
155 to 190
°C
/ W
°C
V
°C
°C
°C
°C
mA
V
V
Symbol
Value
Unit
Notes
1. R = 0
Ω.
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
4. ESD1 performed in accordance with the Human Body Model (C
ZAP
= 100pF, R
ZAP
= 1500
Ω),
ESD2 performed in accordance with the
Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
33790
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V
≤
V
DD
≤
5.25 V, 8.0 V
≤
V
SUP
≤
25.0 V, -40°C
≤
T
J
≤
150°C unless otherwise
noted.
Characteristic
SUPPLY
I
SUP
Supply Current / Channel (Not Including I
OUT
)
DSIx0 = Idle Voltage, -100 mA
≤
I
OUT
≤
0 mA
DSIx0 = Output High Voltage, I
OUT
= 12 mA
I
DD
Supply Current / Channel
BUS TRANSMITTER
V
SUP
to DSIxO ON Resistance (During Idle)
I
OUT
= -100 mA
Output High Voltage
DSIx0 (-15 mA
≤
I
OUT
≤
1.0 mA)
Output Low Voltage
DSIx0 (-15 mA
≤
I
OUT
≤
1.0 mA)
Output High-Side Current Limit
(5)
Output Low-Side Current Limit
(5)
Input Leakage
DSIxO When DSIxF Is High and DSIxS Is Low (0 V
≤
DSIxO
≤
Min
(V
SUP
= 16.5 V))
BUS RECEIVER
Return Current Threshold
MICROCONTROLLER INTERFACE
Logic Input Thresholds DSIxS, DSIxF
Output High Voltage
DSIxR Pin = -0.5 mA
Output Low Voltage
DSIxR Pin = 1.0 mA
Internal Pullup for DSIxF
Internal Pulldown for DSIxS
Notes
5. After 10
µs
settling time (assured by design).
I
IL
I
IH
V
OL
0.0
-100
10
–
–
–
0.2 V
DD
-10
100
µA
µA
V
IN(TH)
V
OH
0.8 V
DD
–
V
DD
V
1.10
–
2.20
V
V
I
RH
- 5.0
- 6.0
- 7.0
mA
I
CLH
I
CLL
DSI
IB
- 200
–
50
DSIV
OL
1.325
- 100
110
1.5
–
–
1.675
-200
220
mA
mA
µA
DSIV
OH
4.175
4.5
4.825
V
R
DS(ON)
–
–
10
V
Ω
I
SUPI
I
SUPH
I
DD
–
–
–
1.35
5.0
0.5
3.25
9.00
1.0
mA
mA
Symbol
Min
Typ
Max
Unit
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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