GS8342R18GE-400T datasheet, PDF

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GS8342R18GE-400T: DescriptionStandard SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165; Categorystorage storage; File Size801KB，33 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8342R18GE-400T Overview

Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165

GS8342R18GE-400T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	STANDARD SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

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Preliminary

GS8342R08/18/36E-400/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

36Mb SigmaCIO DDR-II

Burst of 4 SRAM

167 MHz–400 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaCIO™ Family Overview

The GS8342R08/18/36E are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342R08/18/36E SigmaCIO SRAMs are just

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342R08/18/36E SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs

always transfer data in four packets. When a new address is

loaded, A0 and A1 preset an internal 2 bit linear address

counter. The counter increments by 1 for each beat of a burst of

four data transfer. The counter always wraps to 00 after

reaching 11, no matter where it starts.

Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer

data in four packets. When a new address is loaded, the LSBs

are internally set to 0 for the first read or write transfer, and

incremented by 1 for the next 3 transfers. Because the LSBs

are tied off internally, the address field of a x8 SigmaCIO

DDR-II B4 RAM is always two address pins less than the

advertised index depth (e.g., the 4M x 8 has a 1M addressable

index).

Parameter Synopsis

-400

tKHKH

tKHQV

Rev: 1.00d 1/2004

2.5 ns

0.45 ns

-300

3.3 ns

0.45 ns

1/33

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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