Freescale Semiconductor
Product Preview
Document Number: MC34830
Rev. 1.0, 9/2008
HD to SD Adjustable Bandwidth
Video Buffer with DC Restore
The 34830 is a very high performance video buffer that can handle
HDTV bandwidths up to 1080p resolution. The integrated input clamp
works with all sync formats and all types of video signals. The 34830
includes an innovative capability to set the bandwidth to the optimum
trade-off of performance versus power dissipation. It can be adjusted
all the way from HD frequencies to SD frequencies while benefiting
from the lower power dissipation with lower bandwidths.
The 34830 can drive two standard video loads which are DC or AC
coupled. Input signals can be DC or AC coupled. For the DC coupled
case, the input sync should be close to ground. The 34830 can be
disabled, with shutdown current being 0.12μA.
The 34830 is offered in an ultra thin UDFN package for space critical
applications. It operates on a single 3.0 to 5.5V supply over a -40°C to
85°C temperature range.
Features
•
•
•
•
•
•
•
•
•
•
•
•
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1080p / UXGA to 480i / VGA video buffer with 6dB gain
Integrated input clamp
Adjustable BW to save power
Handles CV, Y, C, Pb, Pr, R, G, B signals
Drives two video loads
Single supply operation
3.0 to 5.5V range
Rail to rail output
0.3% dG / 0.3% dθ for SD
0.6% THD for HD
0.12μA shutdown current
Ultra thin UDFN package
Pb-free packaging designated by suffix code EP
Device
PC34830EP/R2
34830
HD VIDEO BUFFER IC
Bottom
View
EP SUFFIX (PB-FREE)
98ASA10819D
6-PIN UDFN
ORDERING INFORMATION
Temperature
Range (T
A
)
-40°C to 85°C
Package
6-UDFN
Applications
•
•
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Cellular phones
DVD players
Portable Game Players, Set-top boxes
Laptop PCs, Desktop PCs,
Projectors, Digital Cameras, Camcorders, Portable
Media Players, Security Systems
34830
VCC
ENABLE
OUT
IN
RFREQ
GND
Video cable
Figure 1. 34830 Simplified Application Diagram
*This document contains certain information on a product under development. Free-
scale reserves the right to change or discontinue this product without notice
© Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
V
CLAMP
ENABLE
IN
0dB
6dB
OUT
250mV
Levelshift
Bias
Bandwidth
Adjust
RFREQ
GND
Figure 2. 34830 Simplified Internal Block Diagram
34830
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VCC
Transparent
Top View
1
6
EN
IN
GND
2
3
5
4
OUT
RFREQ
Figure 3. 34830 Pin Connections
Table 1. 34830 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 10.
Pin Number
1
2
3
4
5
6
EP
Pin Name
VCC
IN
GND
RFREQ
OUT
EN
-
Pin Function
Power
Input
Ground
Passive
Output
Input
Passive
Formal Name
VCC
Video Input
Ground
Frequency Bandwidth
Set
Video Output
Enable
Exposed Pad
Supply voltage input
Video Input
Ground return for the IC
Connection for the resistor to GND to set operating bandwidth
Video output
Low = device disabled; High = device enabled
Exposed pad for thermal dissipation. Connect the EP to GND or leave
floating. The EP is electrically connected to ground.
Definition
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Maximum Pin Voltage (Except as below)
All other pins -0.3V to Vcc + 0.3V
Maximum Current (into any pin)
THERMAL RATINGS
Ambient Temperature Range
Operating Junction Temperature
Maximum Junction Temperature
Storage Temperature Range
Power Dissipation (UDFN package with EP soldered to ground plane)
T
A
= 25°C
T
A
= 70°C
Thermal Resistance (6-LD UDFN)
θ
JA
θ
JC
Peak Package Soldering Temperature During Reflow
(2)
,
(3)
T
PPRT
70
10
260
°C
1790
1140
°C/W
T
A
T
J
T
JMAX
T
STORE
-40 to 85
-40 to 125
150
-40 to 150
°C
°C
°C
°C
W
±100
mA
V
CC
6.0
V
Symbol
Value
Unit
Notes
1. ESD testing is performed in accordance with the Human Body Model (HBM) (C
ZAP
= 100pF, R
ZAP
= 1500Ω), the Machine Model (MM)
(C
ZAP
= 200pF, R
ZAP
= 0Ω), and the Charge Device Model (CDM), Robotic (C
ZAP
= 4.0pF).
2.
3.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
34830
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions V
CC
= 3.0V to 5.5V, T
A
= -40°C to 85°C, R
FREQ
= 9.0kΩ, C
IN
= 0.1μF, R
L
= 150Ω, C
L
= 5.0pF. Typical values are at T
A
= 27°C, unless otherwise noted.
Characteristic
Input Voltage Range (inferred from gain)
V
CC
= 3V TO 3.4V
V
CC
= 3.4V TO 5.5V
Input Clamping Level
(4)
Output Clamping Level
(5)
Frequency Set Resistor Range
Supply Current measured with no load
R
FREQ
= 108kΩ
R
FREQ
= 9kΩ
Supply Current in Shutdown Mode (EN = 0.0V)
Output Short-circuit Current (Output shorted to V
CC
or ground for <1s)
Input Leakage Current (V
INP
= 1.0V)
Line-Time Distortion (100 IRE, 18μs)
Field-Time Distortion (100 IRE, 18μs, field lines)
Logic Low Input Voltage
Logic High Input Voltage
Logic Level Input Current (source and sink)
I
CCSHUTDOWN
I
SC
I
INP
H
DIST
V
DIST
V
IL
V
IH
I
ILH
V
INPCLAMP
V
OUTCLAMP
R
FREQ
I
CC
-
-
-
-
-
-
-
-
0.7(V
CC
)
-
4.5
17
0.12
100
2.0
0.1
0.2
-
-
-
8
23
5.0
-
5.0
0.2
0.4
0.3(V
CC
)
-
|1.0|
μA
mA
μA
%
%
V
V
μA
Symbol
V
INP
V
INPCLAMP
V
INPCLAMP
-50
400
9.0
-
-
0
500
-
(V
CC
-1)/2
1.2
+50
600
108
mV
mV
kΩ
mA
Min
Typ
Max
Unit
V
Notes
4. Referenced to input. Input clamp not active for signals C, P
b
, P
r
, U, and V.
5.
Establishes output sync level.
34830
Analog Integrated Circuit Device Data
Freescale Semiconductor
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