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QS5991-7TJX

Description
Clock Driver, CMOS, PQCC32
Categorylogic    logic   
File Size122KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

QS5991-7TJX Overview

Clock Driver, CMOS, PQCC32

QS5991-7TJX Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codenot_compliant
JESD-30 codeR-PQCC-J32
JESD-609 codee0
MaximumI(ol)0.046 A
Number of terminals32
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
power supply5 V
Prop。Delay @ Nom-Sup0.7 ns
Certification statusNot Qualified
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Base Number Matches1
QS5991
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with TTL outputs
3 skew grades:
QS5991 -2: t
SKEW0
<250ps
QS5991 -5: t
SKEW0
<500ps
QS5991 -7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50Ω terminated lines
Pin compatible with Cypress CY7B991
Available in PLCC Package
QS5991
DESCRIPTION:
The QS5991 is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The QS5991 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The QS5991 maintains Cypress CY7B991 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (V
CCQ
/PE). When the GND/
sOE
pin is held low, all the outputs are synchronously enabled (CY7B991
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input (CY7B991
compatibility). When V
CCQ
/PE is held low, all the outputs are synchro-
nized with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
G ND/sOE
Skew
Select
3
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3Q
0
3Q
1
Skew
Select
3
3
4F1:0
4Q
0
4Q
1
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c
2000
Integrated Device Technology, Inc.
MARCH 2000
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