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HD75161AP

Description
Octal General Purpose Interface Bus Transceivers
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size245KB,12 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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HD75161AP Overview

Octal General Purpose Interface Bus Transceivers

HD75161AP Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
Parts packaging codeDIP
package instructionDIP,
Contacts20
Reach Compliance Codeunknow
ECCN codeEAR99
Differential outputNO
Number of drives8
Input propertiesSCHMITT TRIGGER
Interface integrated circuit typeLINE TRANSCEIVER
Interface standardsIEEE-488
JESD-30 codeR-PDIP-T20
JESD-609 codee0
length24.5 mm
Number of functions8
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum receive delay22 ns
Number of receiver bits8
Maximum seat height5.08 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
maximum transmission delay20 ns
width7.62 mm
HD75161A
Octal General Purpose Interface Bus Transceivers
REJ03D0309–0200Z
(Previous ADE-205-591 (Z))
Rev.2.00
Jul.16.2004
Description
The HD75161A is an 8 channel general purpose interface bus transceiver designed to meet the requirements of IEEE
standard 488-1978. The transceiver is to provide the bus management and data transfer signals during operating in a
controller instrumentation system. When combined with the HD75160A octal bus transceiver, the HD75161A provides
the complete 16 wire interface for the IEEE 488 bus. The HD75161A features eight driver receiver pairs connected in a
front to back configureation to form input/output ports at both the bus and terminal sides. The direction of data through
these driver receiver pairs is determined by the DC and TE enable signals. The device exhibits a high impedance to the
bus when V
CC
= 0 V since the bus terminating resistors are built in. If featurs driver outputs which can handle loads up
to 48 mA of sink current. Each receiver features p n p transistor inputs for high input impedance and guaranteed
hysteresis of 400 mV for increased noise immunity.
Features
Ordering Information
Part Name
HD75161AP
Package Type
DILP-20 pin
Package Code
DP-20N, -20NEV
P
Package
Abbreviation
Taping Abbreviation
(Quantity)
Pin Arrangement
TE 1
REN 2
IFC 3
GPIB I/O PORTS
NDAC
NRFD
20 V
CC
19 REN
18 IFC
17
16
NDAC
NRFD
TERMINAL I/O PORTS
4
5
DAV 6
EOI 7
ATN 8
SRQ 9
GND 10
15 DAV
14 EOI
13 ATN
12 SRQ
11 DC
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 11

HD75161AP Related Products

HD75161AP HD75161A
Description Octal General Purpose Interface Bus Transceivers Octal General Purpose Interface Bus Transceivers

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