HN58W241000I
Two-wire serial interface
1M EEPROM (128-kword
×
8-bit)
REJ03C0138-0300
Rev.3.00
Jul.12.2005
Description
HN58W241000I is the two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). It realizes
high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology
and CMOS process and low voltage circuitry technology. It also has a 256-byte page programming function to make
it’s write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phone,
camcorders, audio equipment. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
•
•
•
•
Single supply: 2.5 V to 3.6 V
Two-wire serial interface (I
2
C
TM
serial bus*
1
)
Clock frequency: 1 MHz
Power dissipation:
Standby: 1
µA
(max)
Active (Read): 1 mA (max)
Active (Write): 4 mA (max)
Automatic page write: 256-byte/page
Write cycle time: 5.0 ms (max)
Endurance: 10
5
Cycles
Data retention: 10 Years
Small size packages: SOP-8pin (200 mil-wide)
Shipping tape and reel: 1,500 IC/reel
Temperature range:
−40
to +85°C
Lead free products.
•
•
•
•
•
•
•
•
Note: 1. I
2
C is a trademark of Philips Corporation.
Ordering Information
Type No.
HN58W241000FPIE
Internal organization
Operating voltage
1M bit
2.5 V to 3.6 V
(131,072
×
8-bit)
Frequency
1 MHz
Package
200 mil 8-pin plastic SOP
PRSP0008DG-B
(FP-8DFV)
Lead free
Rev.3.00,
Jul.12.2005,
page 1 of 18
HN58W241000I
Pin Arrangement
8-pin SOP
NC
A1
A2
GND
1
2
3
4
8
7
6
5
(Top view)
V
CC
WP
SCL
SDA
Pin Description
Pin name
A1, A2
SCL
SDA
WP
V
CC
V
SS
NC
Device address
Serial clock input
Serial data input/output
Write protect
Power supply
Ground
No connection
Function
Block Diagram
V
CC
V
SS
High voltage generator
Address generator
X decoder
Memory array
WP
A1, A2
SCL
SDA
Control
logic
Y decoder
Y-select & Sense amp.
Serial-parallel converter
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage relative to V
SS
V
CC
Input voltage relative to V
SS
Vin
Operating temperature range*
1
Topr
Storage temperature range
Tstg
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min):
−3.0
V for pulse width
≤
50 ns.
3. Should not exceed V
CC
+ 1.0 V.
Value
−0.6
to +7.0
−0.5*
2
to +7.0*
3
−40
to +85
−65
to +125
Unit
V
V
°C
°C
Rev.3.00,
Jul.12.2005,
page 2 of 18
HN58W241000I
DC Operating Conditions
Symbol
Supply voltage
V
CC
V
SS
Input high voltage
V
IH
Input low voltage
V
IL
Operating temperature
Topr
Notes: 1. V
IL
(min):
−1.0
V for pulse width
≤
50 ns.
2. V
IH
(max): V
CC
+ 1.0 V for pulse width
≤
50 ns.
Parameter
Min
2.5
0
V
CC
×
0.7
−0.3*
1
−40
Typ
0
Max
3.6
0
V
CC
+ 0.5*
2
V
CC
×
0.3
+85
Unit
V
V
V
V
°C
DC Characteristics
(Ta =
−40
to +85°C, V
CC
= 2.5 V to 3.6 V)
Parameter
Input leakage current
Symbol
I
LI
Min
Output leakage current
Standby V
CC
current
Read V
CC
current
Write V
CC
current
Output low voltage
I
LO
I
SB
I
CC1
I
CC2
V
OL
Typ
Max
2.0
20
2.0
1.0
1.0
4.0
0.4
Unit
µA
µA
µA
µA
mA
mA
V
Test conditions
V
CC
= 3.6 V, Vin = 0 to 3.6 V
(SCL, SDA)
V
CC
= 3.6 V, Vin = 0 to 3.6 V
(A1, A2, WP)
V
CC
= 3.6 V, Vout = 0 to 3.6 V
Vin = V
SS
or V
CC
V
CC
= 3.6 V, Read at 1 MHz
V
CC
= 3.6 V, Write at 1 MHz
V
CC
= 2.5 to 3.6 V, I
OL
= 0.8 mA
Capacitance
(Ta = +25°C, f = 1 MHz)
Parameter
Symbol
1
Min
Typ
Max
6.0
6.0
Unit
pF
pF
Test
conditions
Vin = 0 V
Vout = 0 V
Input capacitance (A1 to A2, SCL, WP)
Cin*
Output capacitance (SDA)
C
I/O
*
1
Note: 1. This parameter is sampled and not 100% tested.
Rev.3.00,
Jul.12.2005,
page 3 of 18
HN58W241000I
AC Characteristics
(Ta =
−40
to +85°C, V
CC
= 2.5 to 3.6 V)
Test Conditions
•
Input pules levels:
V
IL
= 0.2
×
V
CC
V
IH
= 0.8
×
V
CC
•
Input rise and fall time:
≤
20 ns
•
Input and output timing reference levels: 0.5
×
V
CC
•
Output load: TTL Gate + 100 pF
V
CC
= 2.5 to 3.6 V
Symbol
Min
Typ
Max
Clock frequency
f
SCL
1000
Clock pulse width low
t
LOW
600
Clock pulse width high
t
HIGH
400
Noise suppression time
t
I
50
Access time
t
AA
100
550
Bus free time for next mode
t
BUF
500
Start hold time
t
HD.STA
250
Start setup time
t
SU.STA
250
Data in hold time
t
HD.DAT
0
Data in setup time
t
SU.DAT
100
Input rise time
t
R
300
Input fall time
t
F
100
Stop setup time
t
SU.STO
250
Data out hold time
t
DH
50
Write protect hold time
t
HD.WP
1000
Write protect setup time
t
SU.WP
0
Write cycle time
t
WC
5.0
Notes: 1. This parameter is sampled and not 100% tested.
2. t
WC
is the time from a stop condition to the end of internally controlled write cycle.
Parameter
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
1
2
Rev.3.00,
Jul.12.2005,
page 4 of 18
Analog electronics
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