STB22NS25Z - STP22NS25Z
N-channel 250V - 0.13Ω - 22A - TO-220 / D
2
PAK
Zener-protected MESH OVERLAY™ Power MOSFET
General features
Type
STB22NS25Z
STP22NS25Z
■
■
V
DSS
250V
250V
R
DS(on)
<0.15Ω
<0.15Ω
I
D
22A
22A
3
100% avalanche tested
Extremely high dv/dt capability
TO-220
1
2
3
1
D²PAK
Description
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an
advanced family of Power MOSFETs with
outstanding performance. The new patented
STrip layout coupled with the Company’s
proprietary edge termination structure, makes it
suitable in coverters for lighting applications.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
STB22NS25Z
STP22NS25Z
Marking
B22NS25Z
P22NS25Z
Package
D²PAK
TO-220
Packaging
Tape & reel
Tube
June 2006
Rev 2
1/14
www.st.com
14
Contents
STB22NS25Z - STP22NS25Z
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
4
5
Test circuits
.............................................. 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/14
STB22NS25Z - STP22NS25Z
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM (1)
P
TOT
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Drain-gate voltage (R
GS
= 20 kΩ)
Gate- source voltage
Drain current (continuos) at T
C
= 25°C
Drain current (continuos) at T
C
= 100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Derating factor
Value
250
250
± 20
22
13.9
88
135
1.07
2500
5
–55 to 150
Max. operating junction temperature
Unit
V
V
V
A
A
A
W
W/°C
V
V/ns
°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
dv/dt
(2)
T
stg
T
j
Peak diode recovery voltage slope
Storage temperature
1. Pulse width limited by safe operating area
2. I
SD
< 22A, di/dt < 200A/µs, V
DD
= 80% V
(BR)DSS
Table 2.
Thermal data
0.93
62.5
300
°C/W
°C/W
°C
Rthj-case Thermal resistance junction-case Max
Rthj-amb Thermal resistance junction-ambient Max
T
l
Maximum lead temperature for soldering purpose
Table 3.
Symbol
I
AR
E
AS
Avalanche Characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25°C, I
D
= I
AR
, V
DD
= 50V, R
g
= 47Ω)
Max value
22
350
Unit
A
mJ
3/14
Electrical characteristics
STB22NS25Z - STP22NS25Z
2
Electrical characteristics
(Tcase =25°C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On /off states
Parameter
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
= 0)
Gate-body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 250µA, V
GS
= 0
V
DS
= Max rating
V
DS
= Max rating, T
C
= 125°C
V
GS
= ±18V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 11A
2
3
0.13
Min.
250
10
100
±10
4
0.15
Typ.
Max. Unit
V
µA
µA
µA
V
Ω
Table 5.
Symbol
g
fs (1)
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Forward
transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 11A
Min.
Typ.
22
2400
340
120
108
11
40
151
Max. Unit
S
pF
pF
pF
nC
nC
nC
V
DS
= 25V, f = 1MHz, V
GS
= 0
V
DD
= 200V, I
D
= 20A,
V
GS
= 10V
(see Figure 13)
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
4/14
STB22NS25Z - STP22NS25Z
Electrical characteristics
Table 6.
Symbol
t
d(on)
t
r
t
d(Voff)
t
f
t
r(Voff)
t
f
t
c
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off- delay time
Fall time
Off-voltage rise time
Fall time
Cross-over time
Test conditions
V
DD
= 125V, I
D
= 11A
R
G
= 4.7Ω V
GS
= 10V
(see Figure 12)
V
DD
= 125V, I
D
= 11 A,
R
G
= 4.7Ω, V
GS
= 10V
(see Figure 12)
V
clamp
= 200V, I
D
= 22 A,
R
G
= 4.7Ω, V
GS
= 10V
(see Figure 12)
Min.
Typ.
20
30
100
78
37
65
110
Max Unit
ns
ns
ns
ns
ns
ns
ns
Table 7.
Symbol
I
SD
I
SDM (1)
V
SD (2)
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 22 A, V
GS
= 0
I
SD
= 22 A, di/dt = 100A/µs
V
DD
= 50V, T
j
= 150°C
(see Figure 17)
292
3065
21
Test conditions
Min.
Typ.
Max. Unit
22
88
1.6
A
A
V
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Table 8.
Symbol
BV
GSO(1)
Gate-source zener diode
Parameter
Gate-source breakdown
voltage
Test conditions
Igs=± 500µA (open drain)
Min
20
Typ
Max Unit
V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components
5/14
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