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UT1750AR12GBAH

Description
16-BIT, 12MHz, RISC PROCESSOR, CPGA144, PGA-144
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size465KB,53 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

UT1750AR12GBAH Overview

16-BIT, 12MHz, RISC PROCESSOR, CPGA144, PGA-144

UT1750AR12GBAH Parametric

Parameter NameAttribute value
Parts packaging codePGA
package instructionPGA,
Contacts144
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Address bus width16
bit size16
boundary scanNO
maximum clock frequency12 MHz
External data bus width16
FormatFLOATING POINT
Integrated cacheNO
JESD-30 codeS-CPGA-P144
length39.751 mm
low power modeNO
Number of terminals144
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height4.826 mm
speed12 MHz
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
total dose1M Rad(Si) V
width39.751 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
Base Number Matches1
Standard Products
UT1750AR RISC Microprocessor
Data Sheet
Jan. 1999
FEATURES
q
Operates in either RISC (Reduced Instruction Set
Computer) mode or MIL-STD-1750A mode
q
Supports MIL-STD-1750A 32-bit floating-point
operations and 48-bit extended-precision
floating-point operations on chip
q
Built-in 9600 baud UART
q
Supports defined MIL-STD-1750A Console Mode of
Operation
q
Full 64K-word address space. Expandable to 1M words with
optional MMU (operand port)
q
Register-oriented architecture has 21 user-accessible
registers
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
M1750
STATE1
MME
NUO3
CONSOLE
RISC
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
q
Registers may be in 16-bit word or 32-bit double-word
configurations
q
Built-in multiprocessor bus arbitration and Direct Memory
Access support (DMA)
q
TTL-compatible I/O
q
Stable 1.5-micron CMOS technology
q
Standard Military Drawing available
q
Full military operating range, -55°C to +125°C,
screened to specific test methods listed in Table I MIL-
STD-883 Method 5004, Class B
16
OSCOUT
OSCIN SYSCLK
UART
OSCILLATOR
/CLOCK
SHIFT REG
PROCESSOR
CONTROL
LOGIC
IR
RISC MAP
32
32
32
8
GENERAL
PURPOSE
REGISTERS
BIT REG
TBR
RBR
TR
16
16
16
16
16
16
16
TIMCLK
TEST
UARTOUT
UARTIN
32
32
32
TB
IM
FR
PI
ST
SW
TEMP DEST
TEMP SRC
I/O
MUX
RISC DATA
RISC
ADDRESS
or O/P DISC
RISC
ADDRESS
SYSFLT
BTERR
MPAR
MPROT
PFAIL
IOLINT1
IOLINT0
INT0-5
MRST
4
16
16
IC/ICs
RISC
ADD
MUX
I
N
T
E
R
R
U
P
T
S
32
ACC
32
16
PIPELINE
PR
A MUX
B MUX
BUS
CONTROL
16
32-BIT ALU
1750 SP
1750 PC
16
32
16
ADDR
MUX
PS0-3
AS0-3
OPERAND
DATA
OP/IN
DTACK
M/IO
R/WR
AS
DS
OPERAND
ADDRESS
4
6
Figure 1. UT1750AR Functional Block Diagram
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