HD74LS645
Octal Bus Transceivers (non-inverted 3-state outputs)
REJ03D0491–0200
Rev.2.00
Feb.18.2005
This octal bus transceivers is designed for asynchronous two-way communication between data buses. The devices
transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction
control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.
Features
•
Ordering Information
Part Name
HD74LS645P
HD74LS645FPEL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
Package
Abbreviation
P
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
PRSP0020DD-B
FP
(FP-20DAV)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
DIR
1A
2A
3A
4A
5A
6A
7A
8A
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Enable
G
1B
2B
3B
4B
5B
6B
7B
8B
(Top view)
Function Table
Enable
G
L
L
H
Note: H; high level, L; low level, X; irrelevant
Direction Control
DIR
L
H
X
Operation
B data to A bus
A data to B bus
Isolation
Rev.2.00, Feb.18.2005, page 1 of 6
HD74LS645
Block Diagram
Enable
G
Transceiver (1/8)
B
A
Direction
Control DIR
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
P
T
Tstg
Ratings
7
7
400
–65 to +150
Unit
V
V
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Symbol
V
CC
I
OH
I
OL
Topr
Min
4.75
—
—
–20
Typ
5.00
—
—
25
Max
5.25
–15
24
75
Unit
V
mA
mA
°C
Rev.2.00, Feb.18.2005, page 2 of 6
HD74LS645
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Hysteresis
Symbol
V
IH
V
IL
V
T+
– V
T–
V
OH
Output voltage
V
OL
Output current
I
OZH
I
OZL
I
IH
I
IL
A or B
I
I
I
OS
***
I
CCH
I
CCL
I
CCZ
V
IK
min.
2.0
—
0.2
2.4
2
—
—
—
—
—
—
—
—
–40
—
—
—
typ.*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
48
62
64
max.
—
0.8
—
—
—
0.4
0.5
20
–400
20
–400
0.1
0.1
–225
70
90
95
Unit
V
V
V
V
µA
µA
µA
mA
mA
mA
V
CC
= 4.75 V
I
OH
= –3 mA
V
CC
= 4.75 V,
V
IH
= 2 V, V
IL
= 0.8 V
I
OH
= –15 mA
I
OL
= 12 mA
V
CC
= 4.75 V,
V
IH
= 2 V, V
IL
= 0.8 V
I
OL
= 24 mA
V
O
= 2.7 V
V
CC
= 5.25 V,
G
input = 2 V
V
O
= 0.4 V
V
CC
= 5.25 V, V
I
= 2.7 V
V
CC
= 5.25 V, V
I
= 0.4 V
V
I
= 5.5 V
V
CC
= 5.25 V
V
I
= 7 V
V
CC
= 5.25 V
V
CC
= 5.25 V, Output open
Condition
Input
current
DIR or
G
Short-circuit output current
Supply current**
Input clamp voltage
—
—
–1.5
V
V
CC
= 4.75 V, I
IN
= –18 mA
Notes: * V
CC
= 5 V, Ta = 25°C
** I
CC
is measured with all outputs open.
*** Not more than one output shall be shorted at a time. the duration of the short circuit shall not exceed one
second.
Switching Characteristics
(V
CC
= 5 V, Ta = 25°C)
Item
Symbol
t
PLH
Propagation delay time
t
PHL
t
ZL
Output enable time
t
ZH
t
LZ
Output disable time
t
HZ
Inputs
A
B
A
B
G
G
G
G
G
G
G
G
Outputs
B
A
B
A
A
B
A
B
A
B
A
B
min.
—
—
—
—
—
—
—
—
—
—
—
—
typ.
8
8
11
11
31
31
26
26
15
15
15
15
max.
15
15
15
15
40
40
40
40
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 5 pF,
R
L
= 667
Ω
Condition
C
L
= 45 pF,
R
L
= 667
Ω
Rev.2.00, Feb.18.2005, page 3 of 6
HD74LS645
Testing Method
Test Circuit
V
CC
4.5V
G
Input
P.G.
Z
out
= 50Ω
R
L
Output
S
1
1A
1B
5kΩ
DIR
C
L
S
2
S
3
Notes:
1.
2.
3.
4.
C
L
includes prove and jig capacitance.
2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, are identical to abobe load circuit.
S
3
is a input-output switch.
All diodes are 1S2074(H).
Waveforms 1
t
TLH
90 %
Input A
(or B)
1.3 V
90 %
1.3 V
10 %
0V
t
THL
3V
10 %
t
PLH
Output B
(or A)
S
1
, S
2
close
1.3 V
t
PHL
1.3 V
See Testing Table
V
OH
V
OL
Note:
Input pulse: t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz, duty cycle 50%
Rev.2.00, Feb.18.2005, page 4 of 6
HD74LS645
Waveforms 2
G
90 %
1.3 V
10 %
t
ZL
Waveform-a
S
1
close
S
2
open
~ 4.5 V
~
1.3 V
V
OL
t
HZ
t
ZH
Waveform-b
S
1
open
S
2
close
V
OH
0.5 V
1.3 V
~
~0V
S
1,
S
2
close
~ 1.5 V
~
V
OH
t
LZ
S
1,
S
2
close
~
~ 1.5 V
V
OL
0V
10 %
t
THL
3V
t
TLH
90 %
1.3 V
0V
3V
0.5 V
Notes:
1. Input pulse: t
TLH
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz, duty cycle 50%
2. Waveform a is an output by internal conditions like "L" except for the case where an output is
disabled by output control.
3. Waveform b is an output by internal conditions like "H" except for the case where an output is
disabled by output control.
Rev.2.00, Feb.18.2005, page 5 of 6
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