HD74LV1GT126ACME datasheet, PDF

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HD74LV1GT126ACME: DescriptionBus Buffer Gate with 3.state Output / CMOS Logic Level Shifter; Categorylogic logic; File Size109KB，8 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74LV1GT126ACME Overview

Bus Buffer Gate with 3.state Output / CMOS Logic Level Shifter

HD74LV1GT126ACME Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	TSSOP, TSSOP5/6,.08
Contacts	5
Reach Compliance Code	compli
Control type	ENABLE HIGH
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G5
JESD-609 code	e0
length	2 mm
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of ports	2
Number of terminals	5
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP5/6,.08
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Prop。Delay @ Nom-Su	13 ns
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1.25 mm

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HD74LV1GT126A

Bus Buffer Gate with 3–state Output /

CMOS Logic Level Shifter

REJ03D0124-0900

Rev.9.00

Mar 21, 2008

Description

The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the

associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE

should be connected to V

through a pull-down resistor; the minimum value of the resistor is determined by the current

sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the

input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from

1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-

speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power

consumption extends the battery life.

Features

•

The basic gate function is lined up as Renesas uni logic series.

•

Supplied on emboss taping for high-speed automatic mounting.

•

TTL compatible input level.

Supply voltage range : 3.0 to 5.5 V

Operating temperature range : –40 to +85°C

•

Logic-level translate function

3.0 V CMOS logic

→

5.0 V CMOS logic (@V

= 5.0 V)

1.8 V or 2.5 V CMOS logic

→

3.3 V CMOS logic (@V

= 3.3 V)

•

All inputs V

(Max.) = 5.5 V (@V

= 0 V to 5.5 V)

All outputs V

(Max.) = 5.5 V (@V

= 0 V, Output : Z)

•

Output current ±6 mA (@V

= 3.0 V to 3.6 V), ±12 mA (@V

= 4.5 V to 5.5 V)

•

All the logical input has hysteresis voltage for the slow transition.

•

Ordering Information

Part Name

HD74LV1GT126ACME

HD74LV1GT126AVSE

Note:

Package Type

CMPAK–5 pin

VSON–5 pin

Package Code

(Previous Code)

PTSP0005ZC-A

(CMPAK-5V)

PUSN0005KA-A

(TNP-5DV)

Package

Abbreviation

Taping Abbreviation

(Quantity)

E (3000 pcs/reel)

Please consult the sales office for the above package availability.

REJ03D0124-0900 Rev.9.00, Mar 21, 2008

Page 1 of 7

HD74LV1GT126ACME Related Products

	HD74LV1GT126ACME	HD74LV1GT126A	GRM1555C2A7R8BA01
Description	Bus Buffer Gate with 3.state Output / CMOS Logic Level Shifter	Bus Buffer Gate with 3.state Output / CMOS Logic Level Shifter	Chip Multilayer Ceramic Capacitors for General Purpose
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	-
Parts packaging code	SOIC	SOIC	-
package instruction	TSSOP, TSSOP5/6,.08	TSSOP,	-
Contacts	5	5	-
Reach Compliance Code	compli	compli	-
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	-
JESD-30 code	R-PDSO-G5	R-PDSO-G5	-
JESD-609 code	e0	e6	-
length	2 mm	2 mm	-
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	-
Number of digits	1	1	-
Number of functions	1	1	-
Number of ports	2	2	-
Number of terminals	5	5	-
Maximum operating temperature	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-
Output characteristics	3-STATE	3-STATE	-
Output polarity	TRUE	TRUE	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSSOP	TSSOP	-
Package shape	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-
propagation delay (tpd)	13 ns	8.5 ns	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	1.1 mm	1.1 mm	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	3 V	4.5 V	-
Nominal supply voltage (Vsup)	3.3 V	5 V	-
surface mount	YES	YES	-
technology	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	-
Terminal form	GULL WING	GULL WING	-
Terminal pitch	0.65 mm	0.65 mm	-
Terminal location	DUAL	DUAL	-
width	1.25 mm	1.25 mm	-

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