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HD74LV32A

Description
Quad. 2-input OR Gates
File Size63KB,9 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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HD74LV32A Overview

Quad. 2-input OR Gates

HD74LV32A
Quad. 2-input OR Gates
REJ03D0311–0300Z
(Previous ADE-205-243A (Z))
Rev.3.00
Jun. 01, 2004
Description
The HD74LV32A has four two-input OR gates in a 14-pin package.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
Package Code
FP–14DAV
FP–14DNV
TTP–14DV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV32AFPEL
HD74LV32ARPEL
HD74LV32ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
A
H
X
L
Note: H: High level
L: Low level
X: Immaterial
B
X
H
L
Output Y
H
H
L
Rev.3.00 Jun. 01, 2004 page 1 of 8

HD74LV32A Related Products

HD74LV32A HD74LV32ATELL HD74LV32ARPEL HD74LV32AFPEL
Description Quad. 2-input OR Gates Quad. 2-input OR Gates Quad. 2-input OR Gates Quad. 2-input OR Gates
Is it lead-free? - Contains lead Contains lead Contains lead
Is it Rohs certified? - incompatible incompatible incompatible
Maker - Renesas Electronics Corporation Renesas Electronics Corporation Renesas Electronics Corporation
Parts packaging code - TSSOP SOIC SOIC
package instruction - TSSOP-14 SOP-14 SOP-14
Contacts - 14 14 14
Reach Compliance Code - unknown unknown unknown
series - LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code - R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
length - 5 mm 8.65 mm 10.06 mm
Load capacitance (CL) - 50 pF 50 pF 50 pF
Logic integrated circuit type - OR GATE OR GATE OR GATE
MaximumI(ol) - 0.006 A 0.006 A 0.006 A
Number of functions - 4 4 4
Number of entries - 2 2 2
Number of terminals - 14 14 14
Maximum operating temperature - 85 °C 85 °C 85 °C
Minimum operating temperature - -40 °C -40 °C -40 °C
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - TSSOP SOP SOP
Encapsulate equivalent code - TSSOP14,.25 SOP14,.25 SOP14,.3
Package shape - RECTANGULAR RECTANGULAR RECTANGULAR
Package form - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE
method of packing - TAPE AND REEL TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) - NOT SPECIFIED 225 NOT SPECIFIED
power supply - 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Sup - 13 ns 13 ns 13 ns
propagation delay (tpd) - 19 ns 19 ns 19 ns
Certification status - Not Qualified Not Qualified Not Qualified
Schmitt trigger - NO NO NO
Maximum seat height - 1.1 mm 1.75 mm 2.2 mm
Maximum supply voltage (Vsup) - 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) - 2 V 2 V 2 V
Nominal supply voltage (Vsup) - 2.5 V 2.5 V 2.5 V
surface mount - YES YES YES
technology - CMOS CMOS CMOS
Temperature level - INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form - GULL WING GULL WING GULL WING
Terminal pitch - 0.65 mm 1.27 mm 1.27 mm
Terminal location - DUAL DUAL DUAL
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width - 4.4 mm 3.95 mm 5.5 mm
Base Number Matches - 1 1 1
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