Features
H
H
H
H
H
H
H
H
5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz (estimated)
Superscalar (3 instructions per clock peak).
Dual 16KB caches.
Selectable bus clock.
32-bit compatibility PowerPC implementation.
On chip debug support.
P
D
typical = 2.5 Watts (200 MHz), full operating conditions.
Nap, doze and sleep modes for power savings.
Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power implementa-
tion of reduced instruction set computer (RISC) microprocessors PowerPC™ family. The 603r is
pin-to-pin compatible with PowerPC 603E and 603P in Cerquad package. The 603r implements
32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of
32 and 64 bits.
The 603r is a low-power design and provides four software controllable power-saving modes.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions
per clock. Instructions can execute out of order for increased performance ; however, the 603r
makes completion appear sequential. The 603r integrates five execution units and is able to exe-
cute five instructions in parallel.
The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction
translation lookaside buffers that provide support for demand-paged virtual memory address
translation and variable-sized block translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface pro-
tocol allows multiple masters to complete for system resources through a central external arbiter.
The 603r supports single-beat and burst data transfers for memory accesses, and supports
memory-mapped I/O.
The 603r uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface
compatibility with TTL devices.
The 603r integrates in system testability and debugging features through JTAG boundary-scan
capability.
TSPC603r
in CERQUAD and
MQUAD Packages
PowerPC 603e
TM
RISC
MICROPROCESSOR
Family PID7t-603e
Specification
Target Specification
Screening / Quality /Packaging
This product is manufactured in full
compliance with:
H
MIL-STD-883 class Q (TBC) or
According to TCS standards
H
Full military temperature range
(T
c
= -55°C, T
c
= +125°C)
Industrial
temperature range
(T
c
= -40°C, T
c
= +110°C)
H
Commercial temperature range
(T
c
= 0°C, T
c
= +70°C)
H
Internal // I/O Power Supply
2.5
±
5 % // 3.3 V
±
5 %
H
240 pin Cerquad or 240 pin
MQUAD packages
MQUAD 240
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity up
Y suffix
MQUAD 240
Metal Quad Flat Pack
Cavity up
August 2000
1/40
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 3
1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. CERQUAD and MQUAD 240 packages . . . . . . . . . . . . 5
2.2. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2. Instruction set and addressing modes . . . . . . . . . . . . . 26
5.2.1. PowerPC instruction set and addressing modes 26
5.2.2. PowerPC 603r microprocessor instruction set . . 27
5.3. Cache implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1. PowerPC cache characteristics . . . . . . . . . . . . . . 27
5.3.2. PowerPC 603r microprocessor cache
implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4. Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.1. PowerPC exception model . . . . . . . . . . . . . . . . . . 28
5.4.2. PowerPC 603r microprocessor exception model 29
5.5. Memory management . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.1. PowerPC memory management . . . . . . . . . . . . . 32
5.5.2. PowerPC 603r microprocessor memory
management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6. Instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . . . . 33
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . . . . . 33
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . 33
8.1. Mechanical dimensions of the wire-bond CERQUAD
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2.
Mechanical dimensions of wire–bond MQUAD
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
B. DETAILED SPECIFICATIONS . . . . . . . . . . . . . . . . . 11
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . 11
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2. Design and construction . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . .
3.2.2. Lead material and finish . . . . . . . . . . . . . . . . . . . . .
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .
3.4. Recommended Operating Conditions . . . . . . . . . . . . .
3.5. Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1. Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2. Thermal management example . . . . . . . . . . . . . .
3.6. Power consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1. Dynamic Power Management . . . . . . . . . . . . . . . .
3.6.2. Programmable Power Modes . . . . . . . . . . . . . . . .
3.6.3. Power Management Modes . . . . . . . . . . . . . . . . .
3.6.4. Power Management Software Considerations . .
3.6.5. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . .
4.1. General requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1. Clock AC specifications . . . . . . . . . . . . . . . . . . . . .
4.3.2. Input AC specifications . . . . . . . . . . . . . . . . . . . . .
4.3.3. Output AC specifications . . . . . . . . . . . . . . . . . . . .
4.4. JTAG AC timing specifications . . . . . . . . . . . . . . . . . . .
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . .
5.1. PowerPC registers and programming model . . . . . . .
5.1.1. General-Purpose Registers (GPRs) . . . . . . . . . . .
5.1.2. Floating-Point Registers (FPRs) . . . . . . . . . . . . . .
5.1.3. Condition Register (CR) . . . . . . . . . . . . . . . . . . . . .
5.1.4. Floating-Point Status and Control Register
(FPSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5. Machine State Register (MSR) . . . . . . . . . . . . . . .
5.1.6. Segment Registers (SRs) . . . . . . . . . . . . . . . . . . .
5.1.7. Special-Purpose Registers (SPRs) . . . . . . . . . . .
11
11
11
11
11
11
12
12
12
12
12
13
13
13
15
15
16
16
16
16
17
17
18
19
21
23
23
23
23
23
23
23
23
23
9. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . . . . . . . . . 36
10. SYSTEM DESIGN INFORMATION . . . . . . . . . . . . . . . . . . 37
10.1. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . 37
10.2. Decoupling Recommendations . . . . . . . . . . . . . . . . . . 37
10.3. Connection Recommendations . . . . . . . . . . . . . . . . . 37
10.4. Pull–up Resistor Requirements . . . . . . . . . . . . . . . . . 37
11. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12. DIFFERENCES WITH COMMERCIAL PART . . . . . . . . . 38
13. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40
TSPC603r
in CERQUAD and MQUAD Packages
TSPC603r
in CERQUAD and MQUAD Packages
A. GENERAL DESCRIPTION
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b
address
64b
data
System Bus
Figure 1 : Block diagram
3/40
1. INTRODUCTION
The 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micropro-
cessors. The 603r implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data
types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architec-
ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603r provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in
nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management
mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without
affecting operational performance, software execution, or any external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute
out of order for increased performance ; however, the 603r makes completion appear sequential.
The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store
unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer instructions execute in one clock
cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data
and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data
and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address
translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The
603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT
and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT
translation takes priority.
The 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to
compete for system resources through a central external arbiter. The 603r provides a three-state coherency protocol that supports the
exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/invalid)
four-state protocol and operates coherently in systems that contain four-state caches. The 603r supports single-beat and burst data
transfers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29
mm
5 metal layer CMOS process technology and maintains full interface compatibility with TTL
devices.
4/40
TSPC603r
in CERQUAD and MQUAD Packages
TSPC603r
in CERQUAD and MQUAD Packages
2. PIN ASSIGNMENTS
2.1. CERQUAD and MQUAD 240 packages
Figure 2 : CERQUAD 240 : Top view
5/40
FPGA/CPLD
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