HN58X2402SI/HN58X2404SI
Two-wire serial interface
2k EEPROM (256-word
×
8-bit)
4k EEPROM (512-word
×
8-bit)
REJ03C0129-0400
Rev.4.00
Jul.13.2005
Description
HN58X24xxSI series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They
realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory
technology and CMOS process and low voltage circuitry technology. They also have a 8-byte page programming
function to make their write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phone,
camcorders, audio equipment. Therefore, please contact Renesas Technology’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I
2
C
TM
serial bus*
1
)
Clock frequency: 400 kHz
Power dissipation:
Standby: 3
µA
(max)
Active (Read): 1 mA (max)
Active (Write): 3 mA (max)
Automatic page write: 8-byte/page
Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V)
Endurance: 10
5
Cycles (Page write mode)
Data retention: 10 Years
Small size packages: TSSOP 8-pin and SOP 8-pin
Shipping tape and reel
TSSOP 8-pin: 3,000 IC/reel
SOP 8-pin: 2,500 IC/reel
Lead free products.
•
•
•
•
•
•
•
Note: 1. I
2
C is a trademark of Philips Corporation.
Ordering Information
Type No.
HN58X2402SFPIE
HN58X2404SFPIE
HN58X2402STIE
HN58X2404STIE
Internal organization
Operating voltage
1.8 V to 5.5 V
2k bit (256
×
8-bit)
4k bit (512
×
8-bit)
2k bit (256
×
8-bit)
4k bit (512
×
8-bit)
1.8 V to 5.5 V
400 kHz
Frequency
400 kHz
Package
150 mil 8-pin plastic SOP
PRSP0008DF-B
(FP-8DBV)
Lead free
8-pin plastic TSSOP
PTSP0008JC-B
(TTP-8DAV)
Lead free
Rev.4.00, Jul.13.2005, page 1 of 17
HN58X2402SI/HN58X2404SI
Pin Arrangement
8-pin TSSOP
8-pin SOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
(Top view)
V
CC
WP
SCL
SDA
Pin Description
Pin name
A0 to A2
SCL
SDA
WP
V
CC
V
SS
Device address
Serial clock input
Serial data input/output
Write protect
Power supply
Ground
Function
Block Diagram
V
CC
V
SS
High voltage generator
Address generator
X decoder
Memory array
WP
A0, A1, A2
SCL
SDA
Control
logic
Y decoder
Y-select & Sense amp.
Serial-parallel converter
Rev.4.00, Jul.13.2005, page 2 of 17
HN58X2402SI/HN58X2404SI
Absolute Maximum Ratings
Parameter
Symbol
Value
−0.6
to +7.0
−0.5*
2
to +7.0*
3
−40
to +85
−65
to +125
Unit
V
V
°C
°C
Supply voltage relative to V
SS
V
CC
Input voltage relative to V
SS
Vin
1
Operating temperature range*
Topr
Storage temperature range
Tstg
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min):
−3.0
V for pulse width
≤
50 ns.
3. Should not exceed V
CC
+ 1.0 V.
DC Operating Conditions
Symbol
Supply voltage
V
CC
V
SS
Input high voltage
V
IH
Input low voltage
V
IL
Operating temperature
Topr
Note: 1. V
IL
(min):
−1.0
V for pulse width
≤
50 ns.
Parameter
Min
1.8
0
V
CC
×
0.7
−0.3*
1
−40
Typ
0
Max
5.5
0
V
CC
+ 1.0
V
CC
×
0.3
+85
Unit
V
V
V
V
°C
DC Characteristics
(Ta =
−40
to +85°C, V
CC
= 1.8 V to 5.5 V)
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Read V
CC
current
Write V
CC
current
Output low voltage
Symbol
I
LI
I
LO
I
SB
I
CC1
I
CC2
V
OL2
Min
Typ
1.0
Max
2.0
20
2.0
3.0
1.0
3.0
0.4
Unit
µA
µA
µA
µA
mA
mA
V
Test conditions
V
CC
= 5.5 V, Vin = 0 to 5.5 V (SCL, SDA)
V
CC
= 5.5 V, Vin = 0 to 5.5 V (A0 to A2, WP)
V
CC
= 5.5 V, Vout = 0 to 5.5 V
Vin = V
SS
or V
CC
V
CC
= 5.5 V, Read at 400 kHz
V
CC
= 5.5 V, Write at 400 kHz
V
CC
= 4.5 to 5.5 V, I
OL
= 1.6 mA
V
CC
= 2.7 to 4.5 V, I
OL
= 0.8 mA
V
CC
= 1.8 to 2.7 V, I
OL
= 0.4 mA
V
CC
= 1.8 to 2.7 V, I
OL
= 0.2 mA
V
OL1
0.2
V
Capacitance
(Ta = +25°C, f = 1 MHz)
Parameter
Symbol
1
Min
Typ
Max
6.0
6.0
Unit
pF
pF
Test
conditions
Vin = 0 V
Vout = 0 V
Input capacitance (A0 to A2, SCL, WP)
Cin*
Output capacitance (SDA)
C
I/O
*
1
Note: 1. This parameter is sampled and not 100% tested.
Rev.4.00, Jul.13.2005, page 3 of 17
HN58X2402SI/HN58X2404SI
AC Characteristics
(Ta =
−40
to +85°C, V
CC
= 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
V
IL
= 0.2
×
V
CC
V
IH
= 0.8
×
V
CC
•
Input rise and fall time:
≤
20 ns
•
Input and output timing reference levels: 0.5
×
V
CC
•
Output load: TTL Gate + 100 pF
Parameter
Symbol
Min
Typ
Max
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Notes
Clock frequency
f
SCL
400
Clock pulse width low
t
LOW
1200
Clock pulse width high
t
HIGH
600
Noise suppression time
t
I
50
Access time
t
AA
100
900
Bus free time for next mode
t
BUF
1200
Start hold time
t
HD.STA
600
Start setup time
t
SU.STA
600
Data in hold time
t
HD.DAT
0
Data in setup time
t
SU.DAT
100
Input rise time
t
R
300
Input fall time
t
F
300
Stop setup time
t
SU.STO
600
Data out hold time
t
DH
50
Write protect hold time
t
HD.WP
1200
Write protect setup time
t
SU.WP
0
Write cycle time
V
CC
= 2.7 V to 5.5 V
t
WC
10
V
CC
= 1.8 V to 2.7 V
t
WC
15
Notes: 1. This parameter is sampled and not 100% tested.
2. t
WC
is the time from a stop condition to the end of internally controlled write cycle.
1
1
1
2
2
Rev.4.00, Jul.13.2005, page 4 of 17
HN58X2402SI/HN58X2404SI
Timing Waveforms
Bus Timing
1/f
SCL
t
LOW
t
R
t
F
SCL
t
SU.STA
t
HD.STA
SDA
(in)
t
AA
SDA
(out)
t
SU.WP
WP
t
HIGH
t
HD.DAT
t
SU.DAT
t
SU.STO
t
BUF
t
DH
t
HD.WP
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
Write data
(Address (n))
ACK
t
WC
(Internally controlled)
Rev.4.00, Jul.13.2005, page 5 of 17
Analogue and Mixed Signal
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