M32C/81 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0031-0100Z
Rev.1.00
Jun. 01, 2004
1. Overview
The M32C/81 group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/81 group is available in 144-pin and 100-
pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili-
ties to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev.1.00 Jun. 01, 2004
page 1 of 83
M32C/81 Group
1. Overview
1.2 Difference between the M32C/81 Group and the M32C/83 Group
The M32/C81 group microcomputer has less peripheral functions than the M32C/83 group
miccrocomputer. The intelligent I/O group 3 and the A/D1 converter are not provided in the M32C/81
group. Interrupt requests, and as a result interrupts, DMAC, and DMACII, caused by intelligent I/O group 3
are not available in the M32C/81 group. However, the A/D1 conversion interrupt is generated in place of the
A/D0 conversion interrupt when input voltage applied to AN0
0
to AN0
7
, AN2
0
to AN2
7
, AN15
0
to AN15
7
pins
are converted.
Rev.1.00 Jun. 01, 2004
page 2 of 83
M32C/81 Group
1. Overview
1.3 Performance Outline
Tables 1.1 and 1.2 list performance outlines of the M32C/81 group.
Table 1.1 M32C/81 Group Performance (144-Pin Package)
CPU
Item
Basic instructions
Shortest instruction execution time
Performance
108 instructions
31.3 ns (f(BCLK)=32 MHz, V
CC
=4.2 V to 5.5 V)
50ns (f(BCLK)=20MHz, V
CC
=3.0 V to 5.5 V)
Single-chip mode, Memory expansion mode and Microprocessor mode
16 Mbytes
See Table 1.3
123 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 12 channels
Waveform generating function: 16 bits x 20 channels
Communication function (Clock synchronous serial I/O, Clock
asynchronous serial I/O, HDLC data processing, Clock synchro-
nous variable length serial I/O, IEBus
(1)
)
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C bus
(2)
1 channel
Supporting CAN 2.0B specification
10-bit A/D converter: 1 circuit, 34 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt factors
Immediate transfer, Calculation transfer and Chain transfer functions
_______
_______
Operation mode
Address space
Memory capacity
Peripheral Port
function Multifunction timer
Intelligent I/O
Serial I/O
CAN module
A/D converter
D/A converter
DMAC
DMAC II
DRAMC
CRC calculation circuit
XY converter
Watchdog timer
Interrupt
Clock generating circuit
Electric
charact-
eristics
Oscillation stop detect function
Supply voltage
Power consumption
Operating ambient temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
CAS-before-RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator
or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 V to 5.5 V (f(BCLK)=32 MHz)
3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC)
28 mA (V
CC
=5 V, f(BCLK)=32 MHz)
17 mA (V
CC
=3.3 V, f(BCLK)=20 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in wait mode)
340
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, through VDC in wait mode)
5.0
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, not through VDC in wait mode)
0.4
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in stop mode)
0.4
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, in stop mode)
–20 to 85
o
C, –40 to 85
o
C (optional)
144-pin plastic molded LQFP
Rev.1.00 Jun. 01, 2004
page 3 of 83
M32C/81 Group
1. Overview
Table 1.2 M32C/81 Group Performance (100-Pin Package)
CPU
Item
Basic instructions
Shortest instruction execution time
Performance
108 instructions
31.3 ns (f(BCLK)=32 MHz, V
CC
=4.2 V to 5.5 V)
50ns (f(BCLK)=20MHz, V
CC
=3.0 V to 5.5 V)
Single-chip mode, Memory expansion mode and Microprocessor mode
16 Mbytes
See Table 1.3
87 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 5 channels
Waveform generating function: 16 bits x 8 channels
Communication function (Clock synchronous serial I/O, Clock
asynchronous serial I/O, HDLC data processing, Clock synchro-
nous variable length serial I/O, IEBus
(1)
)
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C bus
(2)
1 channel
Supporting CAN 2.0B specification
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt factors
Immediate transfer, Calculation transfer and Chain transfer functions
_______
_______
Operation mode
Address space
Memory capacity
Peripheral Port
function Multifunction timer
Intelligent I/O
Serial I/O
CAN module
A/D converter
D/A converter
DMAC
DMAC II
DRAMC
CRC calculation circuit
XY converter
Watchdog timer
Interrupt
Clock generating circuit
Electric
charact-
eristics
Oscillation stop detect function
Supply voltage
Power consumption
Operating ambient temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
CAS-before-RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), sub clock oscillation circuit(*), On-
chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator
or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 V to 5.5 V (f(X
IN
)=32 MHz)
3.0 V to 5.5 V (f(X
IN
)=20 MHz, through VDC)
3.0 V to 3.6 V (f(X
IN
)=20 MHz, not through VDC)
28 mA (V
CC
=5 V, f(BCLK)=32 MHz)
17 mA (V
CC
=3.3 V, f(BCLK)=20 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in wait mode)
340
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, through VDC in wait mode)
5.0
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, not through VDC in wait mode)
0.4
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in stop mode)
0.4
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, in stop mode)
–20 to 85
o
C, –40 to 85
o
C (option)
100-pin plastic molded LQFP/QFP
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev.1.00 Jun. 01, 2004
page 4 of 83
M32C/81 Group
1. Overview
1.4 Block Diagram
Figure 1.1 shows a block diagram of the M32C/81 group microcomputer.
The M32C/81 group microcomputer contains ROM and RAM as memory to store instructions and data,
CPU to execute calculations and peripheral functions such as interrupt, timer, serial I/O, DMAC, CRC
calculation circuit, A/D converter, D/A converter, DRAMC, intelligent I/O and ports.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral functions
Timer (16 bits)
Timer A 5 channels
Timer B 6 channels
Three-phase motor control circuit
Watchdog timer (15 bits)
D/A converter
(8 bits X 2 circuits)
A/D converter
1 circuit
Standard 10 inputs
Maximum 34 inputs
(2)
UART/Clock synchronous serial I/O
5 channels
XY converter
16 bits X 16 bits
CRC calculation circuit (CCITT)
X
16
+X
12
+X
5
+1
Clock generating circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip oscillator
PLL frequency synthesizer
DMAC
DMACII
DRAMC
Intelligent I/O
( 3 groups )
Time measurement 12 channels
(2)
Wave generating 20 channels
(2)
Communication function
Clock synchronous serial I/O, UART,
IEBus, HDLC data processing
M32C/80 series CPU core
R0H
R1H
R2
R3
A0
A1
FB
SB
R0L
R1L
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
ROM
RAM
CAN module
Multiplier
Port P15
Port P14
Port P13
Port P12
Port P11
Port P10
Port P9
P8
5
Port P8
8
7
8
8
5
8
8
7
(Note1)
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
Figure 1.1 M32C/81 Group Block Diagram
Rev.1.00 Jun. 01, 2004
page 5 of 83
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