M32C/83 Group (M32C/83, M32C/83T)
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0013-0141
Rev.1.41
Jan. 31, 2006
1. Overview
The M32C/83 Group (M32C/83, M32C/83T) microcomputer is a single-chip control unit that utilizes high-
performance silicon gate CMOS technology with the M32C/80 Series CPU core. The M32C/83 Group
(M32C/83, M32C/83T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili-
ties to process complex instructions by less bytes and execute instructions at higher speed.
It includes a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments, and other high-speed processing applications.
1.1 Applications
Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
Page 1
of 91
M32C/83 Group (M32C/83, M32C/83T)
1.2 Performance Overview
Tables 1.1 and 1.2 list performance overview of the M32C/83 Group (M32C/83, M32C/83T).
Table 1.1 M32C/83 Group (M32C/83, M32C/83T) Performance (144-Pin Package)
Characteristic
CPU
Basic Instructions
M32C/83
108 instructions
Performance
M32C/83T
Minimum Instruction Execution Time 31.3 ns (f(BCLK)=32 MHz, V
CC
=4.2 to 5.5 V)
(3)
31.3 ns (f(BCLK)=32 MHz, V
CC
=4.2 to 5.5 V)
(3)
50 ns (f(BCLK)=20 MHz, V
CC
=3.0 to 5.5 V)
Operating Mode
Address Space
Memory Capacity
Peripheral I/O Port
Function Multifunction Timer
Intelligent I/O
Single-chip mode, Memory expansion
Single-chip mode
mode and Microprocessor mode
16 Mbytes
See Table 1.3
123 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 12 channels
Waveform generating function: 16 bits x 28 channels
Communication function (Clock synchronous serial I/O, Clock asynchronous se-
rial I/O, HDLC data processing, Clock synchronous variable length serial I/O,
IEBus
(1)
, 8-bit or 16-bit Clock synchronous serial I/O)
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus
(1)
, I
2
C bus
(2)
1 channel Supporting CAN 2.0B specification
10-bit A/D converter: 2 circuit, 34 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CAS before RAS refresh, Self-reflesh, EDO, EP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources, Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator,
PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscilla-
tor must be connected externally
Main clock oscillation stop detect function
4.2 to 5.5 V (f(BCLK)=32 MHz)
4.2 to 5.5 V (f(BCLK)=32 MHz)
3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 to 3.6 V (f(BCLK)=20 MHz,
not through VDC)
41 mA (V
CC
=5 V, f(BCLK)=32 MHz)
41 mA (V
CC
=5 V, f(BCLK)=32 MHz)
38 mA (V
CC
=5 V, f(BCLK)=30 MHz)
38 mA (V
CC
=5 V, Vf(BCLK)=30 MHz)
26 mA (V
CC
=3.3 V, f(BCLK)=20 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz,
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz,
in wait mode)
in wait mode)
0.4
µA
(V
CC
=5 V, stop mode)
340
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz,
through VDC, in wait mode)
5.0
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz,
not through VDC, in wait mode)
0.4
µA
(V
CC
=5 V, stop mode)
0.4
µA
(V
CC
=3.3 V, stop mode)
3.3
±
0.3 V or 5.0
±
0.5 V
5.0
±
0.5 V
100 times
–20 to 85
o
C, –40 to 85
o
C (optional)
–40 to 85
o
C (T version)
144-pin plastic molded LQFP
Serial I/O
CAN Module
A/D Converter
D/A Converter
DMAC
DMAC II
DRAM
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Charact-
eristics
Power Consumption
Flash
Program/Erase Supply Voltage
Memory Program and Erase Endurance
Operating Ambient Temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
3. Contact our sales office if 30-MHz or higher frequency is required.
All options are on a request basis.
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
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M32C/83 Group (M32C/83, M32C/83T)
Table 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance (100-Pin Package)
Characteristic
M32C/83
CPU
Basic Instructions
Minimum Instruction Execution Time
Operating Mode
Address Space
Memory Capacity
I/O Port
Multifunction Timer
Intelligent I/O
Performance
M32C/83T
108 instructions
31.3 ns (f(BCLK) = 32 MHz, V
CC
= 4.2 to 5.5 V)
31.3 ns (f(BCLK) = 32 MHz, V
CC
=4.2 to 5.5 V)
50 ns (f(BCLK) = 20 MHz, V
CC
= 3.0 to 5.5 V)
Single-chip mode, Memory expansion
Single-chip mode
mode and Microprocessor mode
16 Mbytes
See Table 1.3
87 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 5 channels
Waveform generating function: 16 bits x 10 channels
Communication function (Clock synchronous serial I/O, Clock asynchronous se-
rial I/O, HDLC data processing, Clock synchronous variable length serial I/O,
IEBus
(1)
)
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus
(1)
, I
2
C bus
(2)
1 channel Supporting CAN 2.0B specification
10-bit A/D converter: 2 circuits, 26 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator,
PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator
Oscillation Stop Detect Function
Electrical Supply Voltage
Charact-
eristics
Power Consumption
must be connected externally
Main clock oscillation stop detect function
4.2 to 5.5 V (f(BCLK)=32 MHz)
3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC)
41 mA (V
CC
=5 V, f(BCLK)=32 MHz)
38 mA (V
CC
=5 V, f(BCLK)=30 MHz)
26 mA (V
CC
=3.3 V, f(BCLK)=20 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz,
in wait mode)
340
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz,
through VDC, in wait mode)
5.0
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz,
not through VDC, in wait mode)
0.4
µA
(V
CC
=5 V, stop mode)
0.4
µA
(V
CC
=3.3 V, stop mode)
3.3
±
0.3 V or 5.0
±
0.5 V
100 times
–20 to 85
o
C, –40 to 85
o
C (optional)
100-pin plastic molded LQFP/QFP
Peripheral
Function
Serial I/O
CAN Module
A/D Converter
D/A Converter
DMAC
DMAC II
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
4.2 to 5.5 V (f(BCLK)=32 MHz)
41 mA (V
CC
=5 V, f(BCLK)=32 MHz)
38 mA (V
CC
=5 V, Vf(BCLK)=30 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz,
in wait mode)
0.4
µA
(V
CC
=5 V, stop mode)
Flash
Program/Erase Supply Voltage
Memory Program and Erase Endurance
Operating Ambient Temperature
Package
5.0
±
0.5 V
–40 to 85
o
C (T version)
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
3. Contact our sales office if 30-MHz or higher frequency is required.
All options are on a request basis.
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
Page 3 of 91
M32C/83 Group (M32C/83, M32C/83T)
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/83 Group (M32C/83, M32C/83T) microcomputer.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral Functions
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Three-phase Motor Control Circuit
Watchdog Timer (15 bits)
D/A Converter
(8 bits x 2 channels)
A/D Converter:
2 circuits
Standard: 18 inputs
(2)
Maximum: 34 inputs
(2)
UART/Clock Synchronous Serial I/O:
5 channels
X/Y Converter:
16 bits x 16 bits
CRC Calculation Circuit (CCITT):
X
16
+X
12
+X
5
+1
Clock Generation Circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip Oscillator
PLL Frequency Synthesizer
DMAC
DMACII
DRAMC
Intelligent I/O
( 4 Groups )
Time Measurement: 12 channels
(2)
Wave Generating: 28 channels
(2)
Communication Functions:
Clock Synchronous Serial I/O, UART,
IEBus, HDLC Data Processing, 8-bit or
16-bit Clock Synchronous Serial I/O
(3)
CAN Module
M32C/80 Series CPU Core
R0H
R1H
R2
R3
A0
A1
FB
SB
R0L
R1L
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
ROM
RAM
Multiplier
Port P15
Port P14
Port P13
Port P12
Port P11
Port P10
Port P9
P8
5
Port P8
8
7
8
8
5
8
8
7
(Note1)
NOTES:
1. Ports P11 to P15 are provided only in the 144-pin package.
2. Included only in the 144-pin package.
3. Can be used only in the 144-pin package.
Figure 1.1 M32C/83 Group (M32C/83, M32C/83T) Block Diagram
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
Page 4
of 91
M32C/83 Group (M32C/83, M32C/83T)
1.4 Product Information
Table 1.3 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.3 M32C/83 Group (1) (M32C/83)
Type Number
M30835FJGP
M30833FJGP
M30833FJFP
Package Type
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
512K
31K
Flash Memory
ROM
Capacity
As of January, 2006
RAM
Capacity
Remarks
Table 1.3 M32C/83 Group (2) (T Version, M32C/83T)
Type Number
Package Type
ROM
Capacity
As of January, 2006
RAM
Capacity
Remarks
Flash Memory
T Version
(High-reliability
85
o
C Version)
M30833FJTGP
PLQP0100KB-A (100P6Q-A)
512K
31K
Please contact our sales office for V version information.
M30 83 3 F J
GP
Package Type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Package PLQP0144KA-A (144P6Q-A)
Classification:
Blank = General Industrial Use
T = T Version
ROM Capacity:
J = 512 Kbytes
Memory Type:
F = Flash Memory Version
RAM Capacity, Pin Count, etc.
(Value itself has no specific meaning)
M32C/83 Group
M16C Family
Figure 1.2 Product Numbering System
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
Page 5 of 91
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