RQA0014XXDQS
Silicon N-Channel MOS FET
REJ03G1704-0100
Rev.1.00
Oct 20, 2008
Features
•
High output power, High gain, High efficiency
Pout = +28.5 dBm, Linear Gain = 20 dB, PAE = 60% (f = 450 MHz)
•
Suitable for UHF driver stage of high power transmission amplifiers
•
Electrostatic Discharge Immunity Test (IEC Standard 61000-4-2, Level 4)
Outline
RENESAS package code: PLZZ0004CA-A
(Package name: UPAK
R
)
3
2
1
1. Gate
2. Source
4
3. Drain
4. Source
Note:
Marking is “XX”.
*UPAK is a trademark of Renesas Technology Corp.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Channel dissipation
Channel temperature
Storage temperature
Note: Value at Tc = 25°C
Symbol
V
DSS
V
GSS
I
D
Pch
note
Tch
Tstg
Ratings
14
±5
0.3
3
150
–55 to +150
Unit
V
V
A
W
°C
°C
REJ03G1704-0100 Rev.1.00 Oct 20, 2008
Page 1 of 14
RQA0014XXDQS
Electrical Characteristics
(Ta = 25°C)
Item
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Input capacitance
Output capacitance
Reverse transfer capacitance
Output Power
Power Added Efficiency
Symbol
I
DSS
I
GSS
V
GS(off)
Ciss
Coss
Crss
Pout
PAE
Min.
—
—
0.7
—
—
—
27.5
0.56
50
Typ
—
—
1.0
10
6
0.4
28.5
0.71
60
Max.
2
±0.5
1.3
—
—
—
—
—
—
Unit
µA
µA
V
pF
pF
pF
dBm
W
%
Test Conditions
V
DS
= 14 V, V
GS
= 0
V
GS
= ±5 V, V
DS
= 0
V
DS
= 6 V, I
D
= 1 mA
V
GS
= 5 V, V
DS
= 0, f = 1 MHz
V
DS
= 6 V, V
GS
= 0, f = 1 MHz
V
DG
= 6 V, V
GS
= 0, f = 1 MHz
V
DS
= 6 V, I
D
= 50 mA
f = 450 MHz,
Pin = +15 dBm (31.6 mW)
Main Characteristics
Maximum Channel Power
Dissipation Curve
Typical Output Characteristics
1.0
Pulse Test
Channel Power Dissipation Pch (W)
5
Drain Current I
D
(A)
4
0.8
3.0 V
3
0.6
2.5 V
2
0.4
2.0 V
0.2
1.5 V
V
GS
= 1.0 V
1
0
0.0
0
50
100
150
200
0
2
4
6
8
10
Case Temperature T
C
(°C)
Drain to Source Voltage V
DS
(V)
Forward Transfer Admittance
vs. Drain Current
Typical Transfer Characterisitics
Drain Current I
D
(A)
Forward Transfer Admittance |yfs | (S)
Forward Transfer Admittance |yfs| (S)
1.0
V
DS
= 6 V
Pulse Test
1.0
V
DS
= 6 V
Pulse Test
0.8
0.1
0.6
|yfs|
0.4
0.01
0.2
I
D
0.0
0
0.5
1.0
1.5
2.0
2.5
0.001
0.001
0.01
0.1
1.0
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
REJ03G1704-0100 Rev.1.00 Oct 20, 2008
Page 2 of 14
RQA0014XXDQS
Input Capacitance vs.
Gate to Source Voltage
12
10
Output Capacitance vs.
Drain to Source Voltage
12
Output Capacitance Coss (pF)
Input Capacitance Ciss (pF)
10
8
6
4
2
0
-5 -4 -3 -2 -1
0
1
2
3
4
5
V
DS
= 0
f = 1 MHz
8
6
4
2
V
GS
= 0
f = 1 MHz
0
0.1
1
10
Gate to Source Voltage V
GS
(V)
Reverse Transfer Capacitance vs.
Drain to Gate Voltage
1.0
Drain to Source Voltage V
DS
(V)
Reverse Transfer Capacitance Crss (pF)
Maximum Stable Gain MSG (dB)
Maximum Available Gain MAG (dB)
Forward Transfer Coefficient |S21|
2
(dB)
MSG, MAG, |S21|
2
vs. Frequency
30
25
0.8
MSG
MAG
20
15
|S21|
2
0.6
0.4
10
5
V
DS
= 6 V
I
D
= 50 mA
0.2
V
GS
= 0
f = 1 MHz
0
0.1
0
0
500
1000
1
10
1500
2000
Drain to Gate Voltage V
DG
(V)
Maximum Stable Gain, |S21|
2
vs. Drain Current
30
MSG
Frequency f (MHz)
Maximum Stable Gain MSG (dB)
Forward Transfer Coefficient |S21|
2
(dB)
25
20
|S21|
2
15
10
5
0
0
50
100
150
V
DS
= 6 V
f = 450 MHz
Drain Current I
D
(mA)
REJ03G1704-0100 Rev.1.00 Oct 20, 2008
Page 3 of 14
RQA0014XXDQS
Evaluation Circuit (f = 450 MHz)
C6
C5
C9
C10
VG
VD
R1
L2
L4
L3
C7
C8
C1
C2
C3
C4
L1
OUT
IN
C1, C2, C3, C4, C7
C8
C5, C9
C6, C10
: 10 pF Chip Capacitor
: 100 pF Chip Capacitor
: 1000 pF Chip Capacitor
: 10
µF
Chip Capacitor
L1
L2
L3
L4
R1
: 12 nH Chip Inductor
: 1 nH Chip Inductor
: 10 nH Chip Inductor
: 4 turns D: 0.5 mm,
φ2.4
mm Enamel Wire
: 1 kΩ Chip Resistor
REJ03G1704-0100 Rev.1.00 Oct 20, 2008
Page 4 of 14
RQA0014XXDQS
Output Power, Drain Current
vs. Input Power
30
0.3
Pout
0.25
0.2
0.15
0.1
V
DS
= 6 V
I
DQ
= 50 mA
f = 450 MHz
-5
0
5
10
0.05
0.0
15
35
30
Power Gain, Power Added Efficiency
vs. Input Power
Power Gain PG (dB)
Drain Current I
D
(A)
25
20
15
10
5
0
60
PAE
50
25
20
40
I
D
15
10
5
0
-5
0
5
PG
30
20
V
DS
= 6 V
I
DQ
= 50 mA
f = 450 MHz
10
0
15
10
Input Power Pin (dBm)
Input Power Pin (dBm)
PG, PAE vs. Frequency
Input Return Loss vs. Frequency
Power Added Efficiency PAE (%)
20
100
0
Power Gain PG (dB)
16
80
PG
Input Return Loss (dB)
-15
-10
-15
-20
-25
-30
V
DS
= 6 V
I
DQ
= 50 mA
12
PAE
60
8
40
4
20
0
400
450
500
0
400
450
500
Frequency f (MHz)
Frequency f (MHz)
Power Gain vs. Idling Current
Power Added Efficiency
vs. Idling Current
Power Added Efficiency PAE (%)
16
PG
80
16
PG
80
12
PAE
60
12
PAE
60
8
I
DQ
= 50 mA
f = 450 MHz
P
in
= 15 dBm
40
8
I
DQ
= 50 mA
f = 450 MHz
P
in
= 15 dBm
40
4
20
4
20
0
3
4
5
6
7
8
0
0
0
0.05
0.1
0
0.15
Drain to Source Voltage V
DS
(V)
Idling Current I
DQ
(A)
REJ03G1704-0100 Rev.1.00 Oct 20, 2008
Page 5 of 14
Power Added Efficiency PAE (%)
20
100
20
100
Power Gain PG (dBm)
Power Gain PG (dBm)
Power Added Efficiency PAE (%)
70
Output Power Pout (dBm)
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