K7A163601A
K7A161801A
512Kx36 & 1Mx18 Synchronous SRAM
18Mb Sync. Pipelined SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
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* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 3.0 November 2003
K7A163601A
K7A161801A
Document Title
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial draft
1. Add x32 org and industrial temperature .
1. Speed Bin Merge
From K7A1636(32/18)08A to K7A1636(32/18)01A
2. AC parameter change
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
1. Final spec release
1. Release Icc
part #
-25
-22
-20
-16
-14
3.0
From
440
400
370
340
280
To
470
430
400
350
290
Nov. 17, 2003
Final
Draft Date
Feb. 23. 2001
Aug. 30. 2001
Dec. 26. 2001
Remark
Preliminary
Preliminary
Preliminary
1.0
2.0
May. 10. 2002
May. 22. 2002
Final
Final
1. Delete x32 Org.
2. Delelte the 250MHz, 225MHz and 138MHz speed bin.
-2-
Rev. 3.0 November 2003
K7A163601A
K7A161801A
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 2cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A163601A and K7A161801A are 18,874,368-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 512K(1M) words of 36(32/18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A163601A and K7A161801A are fabricated using SAM-
SUNG′s high performance CMOS technology and is available
in a 100pin TQFP package. Multiple power and ground pins are
utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-20
5.0
3.1
3.1
-16
6.0
3.5
3.5
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
512Kx36, 1Mx18
MEMORY
ARRAY
A′
0
~A′
1
A
2
~A
18
or A
2
~A
19
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
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Rev. 3.0 November 2003
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