HD74HCT374, HD74HCT534
Octal D-type Flip-Flops (with 3-state outputs)
Octal D-type Flip-Flops (with inverted 3-state outputs)
REJ03D0667–0200
(Previous ADE-205-556)
Rev.2.00
Mar 30, 2006
Description
These device are positive edge triggered flip-flops. The difference between HD74HCT374 and HD74HCT534 is only
that the former is a true outputs and the latter is a false outputs. Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive going transitions of the clock (CK) input. When a high logic
level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements.
Features
•
•
•
•
•
•
•
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(Clock to Q) = 15 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
HD74HCT374P
HD74HCT374FPEL
HD74HCT534FPEL
HD74HCT374RPEL
HD74HCT534RPEL
HD74HCT374TELL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
TSSOP-20 pin
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
PRSP0020DC-A
(FP-20DBV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
PTSP0020JB-A
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Output Control
Clock
D
L
H
L
L
L
L
X
H
X
X
Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
HD74HCT374
Q
H
L
No change
Z
HD74HCT534
Q
L
H
No change
Z
Rev.2.00 Mar 30, 2006 page 1 of 7
HD74HCT374, HD74HCT534
Pin Arrangement
HD74HCT374
Output
Control 1
1Q
1D
2D
2Q
3Q
3D
4D
4Q
2
3
4
5
6
7
8
9
20 V
CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 Clock
(Top view)
GND 10
HD74HCT534
Output
Control 1
1Q
1D
2D
2Q
3Q
3D
4D
4Q
2
3
4
5
6
7
8
9
20 V
CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 Clock
(Top view)
GND 10
Rev.2.00 Mar 30, 2006 page 2 of 7
HD74HCT374, HD74HCT534
Logic Diagram
HD74HCT374
1D
D Q
C
Q
Clock
2D
D Q
C
Q
3D
D Q
C
Q
4D
D Q
C
Q
5D
D Q
C
Q
6D
D Q
C
Q
7D
D Q
C
Q
8D
D Q
C
Q
Output
Control
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
HD74HCT534
1D
D Q
C
Q
Clock
2D
D Q
C
Q
3D
D Q
C
Q
4D
D Q
C
Q
5D
D Q
C
Q
6D
D Q
C
Q
7D
D Q
C
Q
8D
D Q
C
Q
Output
Control
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
, V
OUT
I
IK
, I
OK
I
OUT
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±20
±35
±75
500
–65 to +150
Unit
V
V
mA
mA
mA
mW
°
C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Input rise / fall time
*1
Symbol
V
CC
V
IN
, V
OUT
Ta
t
r
, t
f
Ratings
4.5 to 5.5
0 to V
CC
–40 to 85
0 to 500
Unit
V
V
°
C
ns
Conditions
V
CC
= 4.5 V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Rev.2.00 Mar 30, 2006 page 3 of 7
HD74HCT374, HD74HCT534
Electrical Characteristics
Item
Input voltage
Output voltage
Symbol V
CC
(V)
V
IH
V
IL
V
OH
V
OL
Off-state output
current
Input current
Quiescent current
I
OZ
Iin
I
CC
Ta = 25°C
Min
Typ
Max
4.5 to 5.5 2.0
—
—
4.5 to 5.5 —
—
0.8
4.5
4.4
—
—
4.5
4.18
—
—
4.5
—
—
0.1
4.5
—
—
0.26
5.5
—
—
±0.5
5.5
5.5
—
—
—
—
±0.1
4.0
Ta = –40 to+85°C
Min
Max
2.0
—
—
0.8
4.4
—
4.13
—
—
0.1
—
0.33
—
±5.0
—
—
±1.0
40
Unit
V
V
V
V
µA
µA
µA
Test Conditions
Vin = V
IH
or V
IL
I
OH
= –20
µA
I
OH
= –6 mA
Vin = V
IH
or V
IL
I
OL
= 20
µA
I
OL
= 6 mA
Vin = V
IH
or V
IL
,
Vout = V
CC
or GND
Vin = V
CC
or GND
Vin = V
CC
or GND, Iout = 0
µA
Switching Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Item
Maximum clock
frequency
Propagation delay time
Output enable time
Output disable time
Setup time
Hold time
Pulse width
Output rise/fall time
Input capacitance
Symbol V
CC
(V)
f
max
t
PLH
t
PHL
t
ZL
t
ZH
t
LZ
t
HZ
t
su
t
h
t
w
t
TLH
t
THL
Cin
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
—
Ta = 25°C
Min
—
—
—
—
—
—
—
20
5
16
—
—
Typ
—
12
15
16
15
13
16
2
0
5
4
5
Max
30
28
28
30
30
30
30
—
—
—
12
10
Ta = –40 to +85°C
Min
—
—
—
—
—
—
—
25
6
20
—
—
Max
24
35
35
38
38
38
38
—
—
—
15
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
Data to clock
Clock to data
Clock, output control
Test Conditions
Test Circuit
V
CC
V
CC
Output
See Function Table
Input
Pulse Generator
Z
out
= 50
Ω
Input
Pulse Generator
Z
out
= 50
Ω
OC
1Q to 8Q
or
1Q to 8Q
1 kΩ
C
L
=
50 pF
S1
OPEN
GND
V
CC
1D to 8D
TEST
t
PLH
/ t
PHL
t
ZH
/ t
HZ
t
ZL
/ t
LZ
S1
OPEN
GND
V
CC
Clock
Note : 1. C
L
includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 7
HD74HCT374, HD74HCT534
Waveforms
•
Waveform –1
t
r
90 % 90 %
1.3 V
10 %
t
r
Input D
90 %
10 %
t
PLH
Output
Q
1.3 V
Output Q
1.3 V
V
OL
10 %
t
f
90 %
10 %
t
PHL
t
f
V
CC
1.3 V
0V
V
CC
Input CLK
0V
V
OH
•
Waveform –2
Input CLK
10 %
t
r
90 % 90 %
1.3 V
1.3 V
t
w
t
su
t
h
t
f
V
CC
1.3 V
10 %
t
w
0V
V
CC
Input D
1.3 V
1.3 V
0V
•
Waveform –3
t
f
90 %
1.3 V
10 %
t
ZL
t
r
90 %
1.3 V
10 %
t
LZ
1.3 V
t
ZH
t
HZ
1.3 V
90 %
V
CC
0V
V
OH
Input OC
Waveform - A
10 %
V
OL
V
OH
V
OL
Waveform - B
Notes : 1. Input waveform : PRR
≤
1 MHz, duty cycle 50%, t
r
≤
6 ns, t
f
≤
6 ns
2. Waveform– A is for an output with internal conditions such that the
output is low except when disabled by the output control.
3. Waveform– B is for an output with internal conditions such that the
output is high except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 5 of 7
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