7547 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0156-0121
Rev.1.21
Nov 15, 2006
DESCRIPTION
The 7547 Group is the QzROM version of 7542 Group.
The 7547 Group has the pin-compatibilty with the 7542 Group. As
new functions, the power-on reset, the low voltage detection cir-
cuit, and the function set ROM are added.
•
•
•
•
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Basic machine-language instructions ...................................... 71
The minimum instruction execution time ............................. 0.25
µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
Memory size
ROM ................................ 8K, 16K bytes
RAM ............................... 384, 512 bytes
Programmable I/O ports ........................................................... 29
Interrupts ................................................. 18 sources, 16 vectors
Timers ............................................................................. 8-bit
✕
2
...................................................................................... 16-bit
✕
2
Output compare ............................................................ 4-channel
Input capture ................................................................ 2-channel
Serial interface ............ 8-bit
✕
2 (UART or Clock-synchronized)
A/D converter ............................................... 10-bit
✕
8 channels
Clock generating circuit ............................................. Built-in type
(low-power dissipation by an on-chip oscillator)
(connected to external ceramic resonator or quartz-crystal
oscillator permitting RC oscillation)
•
•
Watchdog timer ............................................................ 16-bit
✕
1
Power-on reset circuit ............................................... Built-in type
Low voltage detection circuit ..................................... Built-in type
Power source voltage
X
IN
oscillation frequency at ceramic oscillation, in double-speed mode
At 8 MHz .................................................................... 4.5 to 5.5 V
At 6.5 MHz ................................................................. 4.0 to 5.5 V
At 2 MHz .................................................................... 2.4 to 5.5 V
At 1 MHz .................................................................... 2.2 to 5.5 V
X
IN
oscillation frequency at ceramic oscillation, in high-speed mode
or middle-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
At 4 MHz .................................................................... 2.4 to 5.5 V
At 2 MHz .................................................................... 2.2 to 5.5 V
X
IN
oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz .................................................................... 4.0 to 5.5 V
At 2 MHz .................................................................... 2.4 to 5.5 V
At 1 MHz .................................................................... 2.2 to 5.5 V
X
IN
oscillation frequency at on-chip oscillation ......... 1.8 to 5.5 V
Power dissipation ................................................ 29.5 mW (Typ.)
Operating temperature range ................................... –20 to 85 °C
Rev.1.21 Nov 15, 2006
REJ03B0156-0121
page 1 of 89
7547 Group
PIN CONFIGURATION (TOP VIEW)
P1
2
/S
CLK1
P1
3
/S
RDY1
P1
4
/CNTR
0
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
P2
6
/AN
6
P2
7
/AN
7
V
REF
RESET
CNV
SS
Vcc
X
IN
X
OUT
V
SS
1
2
3
4
36
35
34
33
5
6
7
8
9
10
11
12
13
14
15
16
17
18
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P1
1
/T
X
D
1
P1
0
/R
X
D
1
/CAP
0
P0
7
(LED
07
)/S
RDY2
P0
6
(LED
06
)/S
CLK2
P0
5
(LED
05
)/TxD
2
P0
4
(LED
04
)/RxD
2
P0
3
(LED
03
)/TX
OUT
P0
2
(LED
02
)/CMP
1
P0
1
(LED
01
)/CMP
0
P0
0
(LED
00
)/CAP
0
P3
7
(LED
17
)/INT
0
P3
6
(LED
16
)/INT
1
P3
5
(LED
15
)
P3
4
(LED
14
)
P3
3
(LED
13
)/INT
1
P3
2
(LED
12
)/CMP
3
P3
1
(LED
11
)/CMP
2
P3
0
(LED
10
)/CAP
1
Package type: PRSP0036GA-B (36P2R-D)
Fig. 1 Pin configuration (Package type: PRSP0036GA-B)
M37547Gx-XXXFP
M37547GxFP
Rev.1.21 Nov 15, 2006
REJ03B0156-0121
page 2 of 89
7547 Group
Table 1 Performance overview
Parameter
Number of basic instructions
Instruction execution time
Oscillation frequency
Memory sizes
Function
71
0.25
µs
(Minimum instruction, oscillation frequency 8 MHz: double-speed mode)
8 MHz (max.)
ROM
8 K to 16 K bytes
RAM
384 to 512 bytes
I/O port
P0, P1, P2, P3
•8-bit
✕
3, 5-bit
✕
1
Interrupts
18 sources, 16 vectors
Timer
•8-bit
✕
2, 16-bit
✕
2
Output compare
4 channel
Input capture
2 channel
Serial interface
8-bit
✕
2 (UART or clock synchronous)
A/D converter
10-bit
✕
8 channel
Watchdog timer
16-bit
✕
1
Clock generating circuit
Built-in
(external ceramic resonator or quartz-crystal oscillator, RC oscillation available)
(Low consumption current by on-chip oscillator available)
Power source
Double-speed mode At 8MHz oscillation
4.5 to 5.5 V
voltage
At 6.5MHz oscillation 4.0 to 5.5 V
(at ceramic
At 2MHz oscillation
2.4 to 5.5 V
resonance)
At 1MHz oscillation
2.2 to 5.5 V
High-speed mode
At 8MHz oscillation
4.0 to 5.5 V
Middle-speed mode At 4MHz oscillation
2.4 to 5.5 V
Power source
voltage
High-speed mode
Middle-speed mode
At 2MHz oscillation
At 4MHz oscillation
At 2MHz oscillation
2.2 to 5.5 V
4.0 to 5.5 V
2.4 to 5.5 V
2.2 to 5.5 V
1.8 to 5.5 V
29.5 mW (Typ.)
-20 to 85 °C
CMOS sillicon gate
36-pin plastic molded SSOP
(at RC oscillation)
At 1MHz oscillation
Power source voltage (at on-chip oscillation)
Power dissipation
Operating temperature range
Device structure
Package
Rev.1.21 Nov 15, 2006
REJ03B0156-0121
page 3 of 89
FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-B) [7547 Group]
Reset input
V
SS
18
15
13
14
7547 Group
Clock input Clock output
V
CC
CNV
SS
RESET
X
IN
X
OUT
12
26 25 24 23 22 21 20 19
11 10 9 8 7 6 5 4
3 2 1 36 35
34 33 32 31 30 29 28 27
V
REF
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Key-on wakeup
Rev.1.21 Nov 15, 2006
REJ03B0156-0121
CPU
16
17
Clock generating circuit
Fig. 2 Functional block diagram (Package type: PRSP0036GA-B)
page 4 of 89
RAM
X
Prescaler X (8)
CNTR
0
ROM
Y
S
PC
H
PS
PC
L
A
Prescaler 1 (8)
Timer 1 (8)
Timer X (8)
Power-on reset
circuit
Reset
Timer A (16)
Timer B (16)
Low voltage
detection circuit
Reset
Watchdog timer
Reset
0
A/D
converter
(10)
Output
Compare
SI/O2(8)
Input
Capture
SI/O1(8)
INT
0
INT
1
P3(8)
P2(8)
P1(5)
P0(8)
7547 Group
PIN DESCRIPTION
Table 2 Pin description
Name
Pin
Function
Function expect a port function
Power source Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss.
Vcc, Vss
Analog refer- •Reference voltage input pin for A/D converter.
V
REF
ence voltage
CNVss
•Chip operating mode control pin, which is always connected to Vss.
CNVss
Reset input
•Reset input pin for active “L”
RESET
Clock input
•Input and output pins for main clock generating circuit.
X
IN
•Connect a ceramic resonator or quartz crystal oscillator between the X
IN
and X
OUT
pins.
•For using RC oscillator, short between the X
IN
and X
OUT
pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
•When the on-chip oscillator is selected as the main clock, connect X
IN
pin to V
CC
and leave X
OUT
open.
•8-bit I/O port.
• Capture function pin • Key-input
•I/O direction register allows each pin to be individually pro- • Compare function pin (key-on
wake up
grammed as either input or output.
•CMOS compatible input level
• Timer X function pin interrupt
•CMOS 3-state output structure
• Serial I/O2 function pin input) pin
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
• High drive capacity for LED drive port can be selected by program.
•5-bit I/O port
• Serial I/O1 function pin
•I/O direction register allows each pin to be individually pro- • Capture function pin
grammed as either input or output.
• Serial I/O1 function pin
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P1
0
, P1
2
and P1
3
• Timer X function pin
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
• Input pins for A/D converter
X
OUT
Clock output
P0
0
(LED
00
)/CAP
0
I/O port P0
P0
1
(LED
01
)/CMP
0
P0
2
(LED
02
)/CMP
1
P0
3
(LED
03
)/TX
OUT
P0
4
(LED
04
)/RxD
2
P0
5
(LED
05
)/TxD
2
P0
6
(LED
06
)/S
CLK2
P0
7
(LED
07
)/S
RDY2
I/O port P1
P1
0
/RxD
1
/CAP
0
P1
1
/TxD
1
P1
2
/S
CLK1
P1
3
/S
RDY1
P1
4
/CNTR
0
P2
0
/AN
0
–P2
7
/AN
7
I/O port P2
P3
0
(LED
10
)/CAP
1
P3
1
(LED
11
)/CMP
2
P3
2
(LED
12
)/CMP
3
P3
3
(LED
13
)/INT
1
P3
4
(LED
14
)
P3
5
(LED
15
)
P3
6
(LED
16
)/INT
1
P3
7
(LED
17
)/INT
0
I/O port P3
•8-bit I/O port
• Capture function pin
•I/O direction register allows each pin to be individually pro- • Compare function pin
grammed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched • Interrupt input pin
for P3
6
and P3
7
).
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be • Interrupt input pin
determined by program.
• High drive capacity for LED drive port can be selected by program.
Rev.1.21 Nov 15, 2006
REJ03B0156-0121
page 5 of 89
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