BU-61582
SPACE LEVEL MIL-STD-1553
BC/RT/MT
ADVANCED COMMUNICATION
ENGINE (SP’ACE) TERMINAL
FEATURES
Make sure the next
Card you purchase
has...
®
•
Radiation-Hardened to 1 MRad
•
Fully Integrated 1553 Terminal
•
Flexible Processor Interface
•
16K x 16 Internal RAM
•
Automatic BC Retries
•
Programmable BC Gap Times
•
BC Frame Auto-Repeat
•
Intelligent RT Data Buffering
•
Small Ceramic Package
•
Available to SMD 5962-96887
•
Multiple Ordering Options;
+5V (Only)
+5V/-15V
+5V/-12V
+5V/Transceiverless
+5V (Only, with Transmit Inhibits)
DESCRIPTION
DDC’s BU-61582 Space Advanced Communication Engine (SP’ACE)
is a radiation hardened version of the BU-61580 ACE terminal. DDC
supplies the BU-61582 with enhanced screening for space and other
high reliability applications.
The BU-61582 provides a complete integrated BC/RT/MT interface
between a host processor and a MIL-STD-1553 bus. The BU-61582
maintains functional and software compatibility with the standard BU-
61580 product and is packaged in the same 1.9 square-inch package
footprint.
As an option, DDC can supply the BU-61582 with space level screen-
ing. This entails enhancements in the areas of element evaluation and
screening procedures for active and passive elements, as well as the
manufacturing and screening processes used in producing the termi-
nals.
The BU-61582 integrates dual transceiver, protocol, memory man-
agement and processor interface logic, and 16K words of RAM in the
choice of 70-pin DIP or flat pack packages. Transceiverless versions
may be used with an external electrical or fiber optic transceiver.
To minimize board space and ‘glue’ logic, the SP’ACE terminals pro-
vide ultimate flexibility in interfacing to a host processor and inter-
nal/external RAM.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
16K X 16
SHARED
RAM
TRANSCEIVER
A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
DATA
BUFFERS
D15-D0
PROCESSOR
DATA BUS
A15-A0
PROCESSOR
ADDRESS BUS
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
INTERRUPT
REQUEST
CH. A
2
CH. B
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
BU-61582
P-05/08-0
FIGURE 1. BU-61582 BLOCK DIAGRAM
TABLE 1. SP’ACE SERIES SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5V
Transceiver +5V
-15V
-12V
Logic
Voltage Input Range
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35
Ω,
Measured on Bus
Transformer Coupled Across
70
Ω,
Measured on Bus
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
LOGIC
V
IH
V
IL
I
IH
(V
CC
=5.5V, V
IN
=5.5V)
I
IH
(V
CC
=5.5V, V
IN
=0V)
DB15-DB0, A15-A0
RTAD4-RTAD0, RTADP,
MEMWR/ZEROWAIT,
DTREQ/16/8,
DTACK/POLARITY_SEL
All Other Inputs
V
OH
(V
CC
=4.5V, V
IH
=4.2V,
V
IL
=1.0V, I
OH
=max)
V
OL
(V
CC
=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
I
OH
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
BU-61582X0
• +5V (Logic)
BU-61582X1
• +5V (Logic)
• +5V ( Ch. A, Ch. B)
• V
A
V
B
BU-61582X2
• +5V (Logic)
• +5V ( Ch. A, Ch. B)
• V
A
V
B
BU-61582X3/X6 (+5V Only)
• +5V (Logic)
• +5V ( Ch. A, Ch. B)
MIN
TYP
MAX
UNITS
TABLE 1. SP’ACE SERIES SPECIFICATIONS (CONT)
PARAMETER
POWER SUPPLY REQUIREMENTS
(Cont’d)
Current Drain (Total Hybrid)
BU-61582X0
• +5V (Logic)
BU-61582X1
• +5V (Note 10)
-15V
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X2
• +5V (Note 10)
-12V
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X3/X6
(+5V) (Logic, CH. A & CH. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
Total Hybrid
BU-61582X0
BU-61582X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X3/X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
BU-61582X0
BU-61582X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61582X3/X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
-0.5
-0.5
+0.5
+0.5
-0.5
11
7.0
7.0
-18.0
-18.0
Vcc+0.5
V
V
V
V
V
kΩ
50
140
30
68
105
180
140
30
80
130
230
150
240
60
108
160
255
240
60
120
185
305
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
10
0.860
10
pF
Vp-p
Vpeak
6
18
7
20
9
27
10
Vp-p
Vp-p
mVp-p,
diff
mV
nsec
V
V
µA
µA
250
335
460
670
mA
mA
mA
mA
-250
100
3.9
-10
-550
150
250
300
0.250
0.875
1.22
1.475
2.0
0.86
1.16
1.46
2.06
0.750
2.1
2.5
2.97
3.77
1.92
2.35
2.84
3.71
1.34
1.57
1.79
2.23
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
1.3
10
-60
-10
4.0
+10
µA
V
V
mA
mA
0.5
8.0
-8.0
0.225
0.335
0.600
0.860
1.385
0.290
0.590
0.890
1.490
0.50
0.68
1.06
1.45
2.23
0.59
0.92
1.36
2.16
0.28
0.51
0.75
1.22
4.5
5.0
5.5
5.5
5.5
-15.75
5.5
5.5
-12.6
5.25
5.25
V
V
V
V
V
V
V
V
V
4.5
5.0
4.5
5.0
-14.25 -15.0
4.5
4.5
-11.4
4.75
4.75
5.0
5.0
-12.0
5.0
5.0
Data Device Corporation
www.ddc-web.com
3
BU-61582
P-05/08-0
TABLE 1. SP’ACE SERIES SPECIFICATIONS (CONT)
PARAMETER
CLOCK INPUT
Frequency
Nominal Value (programmable)
• Default Mode
• Option
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
Short Term Tolerance,1 second
• 1553A Compliance
• 1553B Compliance
Duty Cycle
• 16 MHz
• 12 MHz
MIN
TYP
MAX UNITS
16.0
12.0
0.01
0.1
0.001
0.01
33
40
67
60
MHz
MHz
%
%
%
%
%
%
µs
µs
19.5
23.5
51.5
131
9
µs
µs
µs
µs
µs
µs
TABLE 1 NOTES (cont)
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5 V logic and transceiver. +5 V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
INTRODUCTION
DDC’s SP’ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9 square inch 70-
pin DIP, surface mountable Flat Pack or Gull Lead, the SP’ACE
series
contains
dual
low-power
transceivers
and
encoder/decoders, complete BC/RT/MT multiprotocol logic,
memory management and interrupt logic, 16K X 16 of shared
static RAM and a direct, buffered interface to a host processor
bus.
The BU-61582 contains internal address latches and bidirection-
al data buffers to provide a direct interface to a host processor
bus. The BU-61582 may be interfaced directly to both 16-bit and
8-bit microprocessors (Please see Appendix G in the ACE User’s
Guide for Product Advisory regarding SP’ACE and SP’ACE II
operating in 8-bit Buffered Non-Zero Wait Mode) in a buffered
shared RAM configuration. In addition, the SP’ACE may connect
to a 16-bit processor bus via a Direct Memory Access (DMA)
interface. The BU-61582 includes 16K words of buffered RAM.
Alternatively, the SP’ACE may be interfaced to as much as 64k
words of external RAM in either the shared RAM or DMA config-
urations.
The SP’ACE RT mode is multiprotocol, supporting MIL-STD-
1553A, MIL-STD-1553B Notice 2, and STANAG 3838 (including
EFAbus).
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The SP’ACE series implements three monitor modes: a word
monitor, a selective message monitor, and a combined RT/selec-
tive monitor.
Other features include options for automatic retries and pro-
grammable intermessage gap for BC mode, an internal Time Tag
Register, an Interrupt Status Register and internal command ille-
galization for RT mode.
1553 MESSAGE TIMING
Completion of CPU Write (BC Start-
2.5
to-Start of Next Message)
BC Intermessage Gap (Note 8)
10.5
BC/RT/MT Response Timeout (Note 9)
18.5 nominal
17.5 18.5
22.5 nominal
21.5 22.5
50.5 nominal
49.5 50.5
128.0 nominal
128 129.5
Transmitter Watchdog Timeout
668
RT Response Timeout (Note 11)
4
6.5
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θ
JC
)
BU-61582X0
BU-61582X1
BU-61582X2
BU-61582X3/X6
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
70-pin DIP, Flat Pack
J-Lead, Gull Leads
Weight
70-pin DIP, Flat Pack
J-Lead, Gull Leads
4.6
7.2
7.2
12
-55
-65
150
150
+300
°C/W
°C/W
°C/W
°C/W
°C
°C
°C
1.9 X 1.0 X 0.215
(48.26 x 25.4 x 5.46
0.6
(7)
in.
(mm)
oz
(g)
TABLE 1 NOTES: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the SP'ACE Series hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed, but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535 µs minus message time), in
increments of 1 µs.
Data Device Corporation
www.ddc-web.com
4
BU-61582
P-05/08-0
FUNCTIONAL OVERVIEW
TRANSCEIVERS
For the +5 V and -15 V/-12 V front end, the BU-61582X1(X2)
uses low-power bipolar analog monolithic and thin-film hybrid
technology. The transceiver requires +5 V and -15 V (-12 V) only
(requiring no +15 V/+12 V) and includes voltage source trans-
mitters. The voltage source transmitters provide superior line
driving capability for long cables and heavy amounts of bus load-
ing.
The receiver sections of the BU-61582 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage pro-
tection, threshold, common mode rejection, and word error
rate. In addition, the receiver filters have been designed for
optimal operation with the J-Rad chip’s Manchester II
decoders.
For interfacing to fiber optic transceivers for MIL-STD-1773
applications, a transceiverless version of the SP’ACE can be
used. These versions provide a register programmable option for
a direct interface to the single-ended outputs of a fiber optic
receiver. No external logic is needed.
TIME TAGGING
The SP’ACE includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs per
LSB. Also, the Time Tag Register may be clocked from an exter-
nal oscillator. Another option allows software controlled incre-
menting of the Time Tag Register. This supports self-test for the
Time Tag Register. For each message processed, the value of
the Time Tag register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for both
BC and RT modes.
Additional provided options will: clear the Time Tag Register fol-
lowing a Synchronize (without data) mode command or load the
Time Tag Register following a Synchronize (with data) mode
command; enable an interrupt request and a bit setting in the
Interrupt Status Register when the Time Tag Register rolls over
from FFFF to 0000. Assuming the Time Tag Register is not
loaded or reset, this will occur at approximately 4 second time
intervals, for 64 µs/LSB resolution, down to 131 ms intervals,
for 2 µs/LSB resolution.
Another programmable option for RT mode is the automatic clear-
ing of the Service Request Status Word bit following the
BU-61582’s response to a Transmit Vector Word mode command.
J-RAD DIGITAL MONOLITHIC
The J-Rad digital monolithic represents the cornerstone element
of the BU-61582 SP’ACE family of terminals. The J-Rad chip is
actually a radiation hardened version of DDC’s J’ (J-prime)
monolithic which is the key building block behind DDC’s non-radi-
ation hardened BU-61580 ACE series of terminals. As such, the
J-Rad possesses all the enhanced hardware and software fea-
tures which have made the BU-61580 ACE the industry standard
1553 interface component.
The J-Rad chip consists of a dual encoder/decoder, complete
protocol for Bus Controller (BC), 1553A/B/McAir Remote
Terminal (RT), and Monitor (MT) modes; memory management
and interrupt logic; a flexible, buffered interface to a host proces-
sor bus and optional external RAM; and a separate buffered
interface to external RAM. Reference the region within the dotted
line of FIGURE 1. Besides realizing all the protocol, memory
management, and interface functions of the earlier AIM-HY
series, the J-Rad chip includes a large number of enhancements
to facilitate hardware and software design, and to further off-load
the 1553 terminal’s host processor.
DECODERS
The default mode of operation for the BU-61582 BC/RT/MT
requires a 16 MHz clock input. If needed, a software program-
mable option allows the device to be operated from a 12 MHz
clock input. Most current 1553 decoders sample using a 10 MHz
or 12 MHz clock. In the 16 MHz mode (default following a hard-
ware or software reset), the decoders sample 1553 serial data
using the 16 MHz clock. In the 12 MHz mode (or 16 MHz), the
decoders can be programmed to sample using both clock edges;
this provides a sampling rate of 24 MHz. The faster sampling rate
for the J-Rad’s Manchester II decoders provides superior per-
formance in terms of bit error rate and zero-crossing distortion
tolerance.
INTERRUPTS
The SP’ACE series components provide many programmable
options for interrupt generation and handling. The interrupt out-
put pin INT has three software programmable modes of opera-
tion: a pulse, a level output cleared under software control, or a
level output automatically cleared following a read of the
Interrupt Status Register. Individual interrupts are enabled by the
Interrupt Mask Register. The host processor may easily deter-
mine the cause of the interrupt by using the Interrupt Status
Register. The Interrupt Status Register provides the current state
of the interrupt conditions. The Interrupt Status Register may be
updated in two ways. In the standard interrupt handling mode, a
particular bit in the Interrupt Status Register will be updated only
if the condition exists and the corresponding bit in the Interrupt
Mask Register is enabled. In the enhanced interrupt handling
mode, a particular bit in the Interrupt Status Register will be
updated if the condition exists regardless of the contents of the
corresponding Interrupt Mask Register bit. In any case, the
respective Interrupt Mask Register bit enables an interrupt for a
particular condition.
Data Device Corporation
www.ddc-web.com
5
BU-61582
P-05/08-0
FPGA/CPLD
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