HD74HC192, HD74HC193
Synchronous Up/Down Decade Counter (Dual Clock Lines)
Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines)
REJ03D0588-0300
Rev.3.00
Jan 31, 2006
Description
The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock
inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low
to high transition of either clock while the other input is held high. The direction of counting is determined by which
input is clocked.
These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the
load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be
used as divide-by-n counters by modifying the count length with the preset inputs.
In addition both counters can also be cleared. This is accomplished by inputting a high on the clear input. All 4 internal
stages are set to a low level independently of either count input.
Both a borrow and carry output are provided to enable cascading of both up and down counting functions. The borrow
output produces a negative going pulse when the counter underflows and the carry outputs a pulse when the counter
overflows. The counters can be cascaded by connecting the carry and borrow outputs of one device to the count up and
count down inputs, respectively, of the next device.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock Up or Count Down to Q) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
—
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
HD74HC192P
PRDP0016AE-B
DILP-16 pin
P
(DP-16FV)
HD74HC193P
HD74HC192FPEL
PRSP0016DH-B
SOP-16 pin (JEITA)
FP
(FP-16DAV)
HD74HC193FPEL
Note: Please consult the sales office for the above package availability.
Rev.3.00, Jan 31, 2006 page 1 of 13
HD74HC192, HD74HC193
Timing Chart
HD74HC192
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to binary seven.
Count up to eight, nine, zero, one and two.
Count down to one, zero, borrow, nine, eight and seven.
Clear
Load
A
Data
Inputs
B
C
D
Count Up
Count Down
Q
A
Q
B
Q
C
Q
D
Carry
Borrow
8
Sequence
Illustrated
0
Clear
7
Preset
9
0
1
2
1
0
9
8
7
Count Up
Count Down
Rev.3.00, Jan 31, 2006 page 3 of 13
HD74HC192, HD74HC193
Timing Chart
HD74HC193
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen, zero, one and two.
Count down to one, zero, borrow, fifteen and thirteen.
Clear
Load
A
Data
Inputs
B
C
D
Count Up
Count Down
Q
A
Q
B
Outputs
Q
C
Q
D
Carry
Borrow
0
13
14
15
0
1
2
1
0
15
14
13
Count Up
Clear
Preset
Count Down
Rev.3.00, Jan 31, 2006 page 4 of 13
京公网安备 11010802033920号
EEWORLD
