HD74HC175
Quad. D-type Flip-Flops (with Clear)
REJ03D0585-0300
Rev.3.00
Jan 31, 2006
Description
Information at the D inputs of the HD74HC175 is transferred to the Q and
Q
outputs on the positive going edge of the
clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip-flops are
controlled by a common clock and a common clear. Clearing is accomplished by a negative pulse at the clear input.
All four Q outputs are cleared to a logic low level and all four
Q
outputs to a logic high level.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC175P
Package Type
DILP-16 pin
Package Code
(Previous Code)
Package
Abbreviation
—
ELL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
PRDP0016AE-B
P
(DP-16FV)
PTSP0016JB-A
HD74HC175TELL
TSSOP-16 pin
T
(TTP-16DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Clear
L
H
H
H
High level
Low level
Irrelevant
Inputs
Clock
X
Output
D
X
H
L
X
Q
L
H
L
no change
Q
H
L
H
L
H:
L:
X:
Rev.3.00, Jan 31, 2006 page 1 of 6
HD74HC175
Pin Arrangement
Clear 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
(Top view)
D
CK
Q
CLR
Q
D
Q
CK
CLR
Q
Q
CLR
CK
Q
D
CLR
Q
CK
Q
D
16 V
CC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 Clock
Logic Diagram
1D
D
CK
Clock
2D
CK CL
D
CK
CK CL
3D
D
CK
CK CL
4D
D
CK
CK CL
Clear
4Q
Q
3Q
Q
2Q
Q
1Q
2Q
Q
1Q
3Q
4Q
Rev.3.00, Jan 31, 2006 page 2 of 6
HD74HC175
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Storage temperature
Symbol
V
CC
Vin, Vout
I
IK
, I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±20
±25
±50
500
–65 to +150
Unit
V
V
mA
mA
mA
mW
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Input rise / fall time
Note:
*1
Symbol
V
CC
V
IN
, V
OUT
Ta
t
r
, t
f
Ratings
2 to 6
0 to V
CC
–40 to 85
0 to 1000
0 to 500
0 to 400
Unit
V
V
°C
ns
Conditions
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item
Input voltage
Symbol V
CC
(V)
V
IH
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Ta = 25°C
Min
Typ Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
—
—
—
—
—
—
2.0
4.5
6.0
—
—
0.0
0.0
0.0
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta = –40 to+85°C
Unit
Min
Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
V
Test Conditions
V
IL
V
Output voltage
V
OH
V
Vin = V
IH
or V
IL
I
OH
= –20
µA
V
OL
V
Vin = V
IH
or V
IL
I
OH
= –4 mA
I
OH
= –5.2 mA
I
OL
= 20
µA
Input current
Quiescent supply
current
Iin
I
CC
I
OL
= 4 mA
I
OL
= 5.2 mA
µA
Vin = V
CC
or GND
µA
Vin = V
CC
or GND, Iout = 0
µA
Rev.3.00, Jan 31, 2006 page 3 of 6
HD74HC175
Switching Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Symbol V
CC
(V)
f
max
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
Ta = 25°C
Ta = –40 to +85°C
Unit
Min
Typ Max
Min
Max
—
—
—
—
—
—
—
—
—
100
20
17
5
5
5
100
20
17
80
16
14
—
—
—
—
—
—
—
—
14
—
—
14
—
—
3
–
—
–1
—
—
–1
—
—
9
—
—
5
—
5
6
30
35
150
30
26
185
37
31
—
—
—
—
—
—
—
—
—
—
—
—
75
15
13
10
—
—
—
—
—
—
—
—
—
125
25
21
5
5
5
125
25
21
100
20
17
—
—
—
—
5
24
28
190
38
33
230
46
39
—
—
—
—
—
—
—
—
—
—
—
—
95
19
16
10
MHz
Test Conditions
t
PLH
, t
PHL
ns
Clock to Q or
Q
ns
Clear to Q or
Q
Setup time
t
su
ns
Data to Clock
Hold time
t
h
ns
Clock to Data
Removal time
t
rem
ns
Clear to Clock
Pulse width
t
w
ns
Clock, Clear
Output rise/fall
time
Input capacitance
t
TLH
, t
THL
ns
Cin
pF
Test Circuit
Measurement point
C
L*
Note: C
L
includes the probe and fig capacitance.
Rev.3.00, Jan 31, 2006 page 4 of 6
HD74HC175
Waveforms
•
Waveform – 1
t
r
90 %
50 %
10 %
90 %
50 %
10 %
50 %
t
f
V
CC
0V
Data
t
su
t
r
Clock
10 %
t
h
t
f
90 %
50 %
50 %
10 %
t
su
t
h
V
CC
50 %
t
w
t
PLH
Q
10 %
90 %
50 %
t
w
t
PHL
90 %
50 %
10 %
0V
V
OH
V
OL
t
TLH
t
PHL
Q
50 %
10 %
t
THL
t
PLH
90 %
50 %
10 %
V
OH
V
OL
t
THL
t
TLH
•
Waveform – 2
90 %
50 %
10 %
t
f
t
r
90 %
50 %
10 %
t
w
t
f
90 %
50 %
10 %
t
w
90 %
50 %
10 %
t
THL
t
PLH
90 %
t
r
90 %
50 %
10 %
t
PLH
90 %
50 %
10 %
t
TLH
t
PHL
90 %
50 %
10 %
t
THL
V
OH
V
OL
V
OL
V
OH
V
CC
0V
V
CC
0V
Clear
Clock
t
rem
t
PHL
Q
Q
50 %
10 %
t
TLH
Note : Clock Input : PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
Data Input : PRR
≤
500 kHz
Rev.3.00, Jan 31, 2006 page 5 of 6
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