Bt121
Monolithic CMOS Triple 8-Bit VIDEODAC
The Bt121 is a triple 8-bit VIDEODAC designed specifically for
high-performance, high-resolution color graphics.
This device offers a higher level of integration than previous VIDEODAC
designs. Included is an on-chip voltage reference to simplify use of the
device.
The Bt121 generates RS-343A-compatible video signals into a
doubly-terminated 75
Ω
load, and RS-170-compatible video signals into a
singly-terminated 75
Ω
load, without requiring external buffering. Both the
differential and integral linearity errors of the D/A converters are guaranteed
to be a maximum of ±1 LSB over the full temperature range.
Product Features
• 80, 50 MHz Operation
• Triple 8-bit D/A Converters
• Optional Internal Voltage
Reference
• RS-343A-Compatible Outputs
• TTL-Compatible Inputs
• +5 V CMOS Monolithic
Construction
• 44-pin PLCC Package
• Typical Power Dissipation:
600 mW
Functional Block Diagram
Applications
•
•
•
•
•
COMP
VREF FS ADJUST
Reference
Amplifier
High-Resolution Color Graphics
CAE/CAD/CAM
Image Processing
Video Reconstruction
Instrumentation
CLOCK
8
R0-R7
1.2 V
8
DAC
IOR
8
G0-G7
8
B0-B7
SYNC*
BLANK*
R
E
G
I
S
T
E
R
8
DAC
IOG
8
DAC
IOB
VAA
AGND
L121001, Ref. G
Circuit Description
As illustrated in the functional block diagram, the Bt121 contains three 8-bit D/A converters, input
registers, and a reference amplifier.
On the rising edge of CLOCK, 24 bits of color information (R0–R7, G0–G7, and B0–B7) are
latched into the device and presented to the three 8-bit D/A converters.
Latched on the rising edge of CLOCK to maintain synchronization with the color data, the
SYNC* and BLANK* inputs add appropriately weighted currents to the analog outputs, producing
the specific output levels required for video applications as illustrated in Figure 1. Table 1 details
how the SYNC* and BLANK* inputs modify the output levels.
The D/A converters on the Bt121 use a segmented architecture in which bit currents are routed
to either the output or GND by a sophisticated decoding scheme. This architecture eliminates the
need for precision component ratios and greatly reduces the switching transients associated with
turning current sources on or off. Monotonicity and low glitch are guaranteed by use of identical
current sources and current steering their outputs. An on-chip operational amplifier stabilizes the
full-scale output current against temperature and power supply variations.
The analog outputs of the Bt121 can directly drive a 37.5
Ω
load, such as a doubly-terminated
75
Ω
coaxial cable.
ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device damage, which can
produce symptoms of catastrophic failure or erratic device behavior with somewhat leaky inputs.
All logic inputs should be held low until power to the device has settled to the specified
tolerance. DAC power decoupling networks with large time constants should be avoided. They
could delay VAA power to the device. Ferrite beads must only be used for analog power VAA
decoupling. Inductors cause a time constant delay that induces latchup.
Latchup can be prevented by ensuring that all VAA pins are at the same potential and that the
VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence
ensures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V
.
2
L121001, Ref. G
Bt121
Monolithic CMOS Triple 8-Bit VIDEODAC
Circuit Description
ESD and Latchup Considerations
Figure 1. Composite Video Output Waveforms
NO SYNC
MA
V
MA
SYNC
V
19.05
0.714
26.67
1.000
WHITE LEVEL
92.5 IRE
1.44
0.00
0.054
0.000
9.05
7.62
0.340
7.5 IRE
BLACK LEVEL
0.286
40 IRE
BLANK LEVEL
0.00
0.000
SYNC LEVEL
Note: 75
Ω
doubly-terminated load, RSET ~ 143
Ω,
and VREF = 1.23 V. RS-343A levels and tolerances are assumed
on all levels.
Table 1. Video Output Truth Table
Description
WHITE
DATA
DATA-SYNC
BLACK
BLACK-SYNC
BLANK
SYNC
Iout (mA)
26.67
data + 9.05
data+1.44
9.05
1.44
7.62
0
SYNC
1
1
0
1
0
1
0
BLANK
1
1
1
1
1
0
0
DAC Input Data
$FF
data
data
$00
$00
$xx
$xx
Note: 75
Ω
a doubly-terminated load, SETUP = 7.5 IRE. VREF = 1.23 V and RSET ~ 143
Ω
.
L121001, Ref. G
3
Circuit Description
ESD and Latchup Considerations
Bt121
Monolithic CMOS Triple 8-Bit VIDEODAC
Table 2. Pin Descriptions
Pin Name
BLANK*
Description
Composite blank control input (TTL compatible). A logical zero drives the IOR, IOG, and IOB
outputs to the blanking level, as detailed in Table 1. BLANK* is latched on the rising edge of
CLOCK. When BLANK* is a logical zero, the R0–R7, G0–G7, and B0–B7 inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on this input switches off a 40
IRE current source on the IOR, IOG, IOB outputs (see Figure 1). SYNC* does not override
any other control or data input, as shown in Table 1; therefore, SYNC* should be asserted
only during the blanking interval. It is latched on the rising edge of CLOCK.
Red, green, and blue data inputs (TTL compatible). R0, G0, and B0 are the least-significant
data bits. They are latched on the rising edge of CLOCK. Coding is binary.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC*, and BLANK* inputs. It is typically the pixel clock rate of the video system. It is recom-
mended that the CLOCK input be driven by a dedicated TTL buffer to avoid reflection-induced
jitter.
Red, green, and blue current outputs. These high-impedance current sources can directly
drive a doubly-terminated 75
Ω
coaxial cable (see Figure 3 and Figure 4 in the PC Board Lay-
out Considerations section). All outputs, whether used or not, should have the same output
load.
Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the
magnitude of the full-scale video signal (Figure 1). The IRE relationships are maintained,
regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on IOR, IOG and IOB is:
RSET (
Ω
) = K * VREF (V) /IO (mA)
Where; K = 2,295 with SYNC*= 0
K = 3,195 with SYNC*= 1
SYNC*
R0–R7, G0–07,
B0–B7
CLOCK
IOR, IOG, IOB
FS ADJUST
COMP
Compensation pin. This pin provides compensation for the internal reference amplifier. A
0.1 µF ceramic capacitor in series with a resistor should be connected between this pin and
the nearest VAA pin (Figure 3 and Figure 4) for optimum settling time. Connecting the capaci-
tor to VAA rather than to GND provides the highest possible power supply noise rejection. The
COMP resistor and capacitor must be as close to the device as possible to keep lead lengths
to an absolute minimum. Refer to the PC Board Layout Considerations section for critical lay-
out criteria.
Voltage reference input. If an external voltage reference is used (Figure 4), it must supply this
input with a 1.2 V (typical) reference. A 0.1 µF ceramic capacitor must always be used to
decouple this input to GND. The decoupling capacitor must be as close to the device as pos-
sible to keep lead lengths to an absolute minimum. When the internal reference is used, this
pin should not drive any external circuitry, except the decoupling capacitor (Figure 3).
Analog ground. All GND pins must be connected together on the same PCB plane to prevent
latchup.
Analog power. All VAA pins must be connected together on the same PCB plane to prevent
latchup.
VREF
GND
VAA
4
L121001, Ref. G
Bt121
Monolithic CMOS Triple 8-Bit VIDEODAC
Circuit Description
ESD and Latchup Considerations
Figure 2. Pin Diagram
FS ADJUST
COMP
VREF
GND
GND
30
39
38
37
36
35
34
33
32
31
29
GND
VAA
VAA
IOG
IOR
IOB
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
SYNC*
40
41
42
43
44
1
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
10
11
12
13
14
15
16
GND
BLANK
L121001, Ref. G
GND
G7
G6
G5
G4
G3
G2
G1
G0
17
7
8
9
5
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