To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
M35053-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
The M35053-XXXSP/FP is TV screen display control IC which can
be used to display information such as number of channels, the date
and messages and program schedules on the TV screen.
In particular, owing to the built-in SYNC-SEP (synchronous separa-
tion) circuit, the synchronous correction circuit, the Decoder circuit,
and to the Encoder circuit, external circuits can be decrease and
character turbulence that occurs when superimposing can be reduced.
The processor can conform to the EDS broadcast service and is suit-
able for AV systems such as VTRs, LDs, and so on.
It is a silicon gate CMOS process and M35053-XXXSP is housed in
a 20-pin shrink DIP package, M35053-XXXFP is housed in a 20-pin
shrink SOP package.
For M35053-001SP/FP that is a standard ROM version of M35053-
XXXSP/FP respectively, the character pattern is also mentioned.
PIN CONFIGURATION (TOP VIEW)
CP1
TESTA
CS
←
→
→
↔
→
1
2
3
20
19
18
V
DD1
SCK
SIN
AC
4
5
6
7
17
16
15
14
13
12
11
←
HOR
→
CP2
←
OSCIN
V
SS
M35053-XXXSP
V
DD2
CVIDEO
LECHA
CVIN
→
P1
→
P0
TESTB
FEATURES
←
→
→
8
9
10
→
EDO
V
SS
•
Screen composition .............................. 24 characters
✕
10 lines,
•
•
•
•
•
•
•
•
•
32 characters
✕
7 lines
Number of characters displayed .................................. 240 (Max.)
Character composition ..................................... 12
✕
18 dot matrix
Characters available ............................................. 256 characters
Character sizes available .................... 4 (horizontal)
✕
4 (vertical)
Display locations available
Horizontal direction ............................................... 240 locations
Vertical direction ................................................... 256 locations
Blinking ................................................................. Character units
Cycle : approximately 1 second, or approximately 0.5 seconds
Duty : 25%, 50%, or 75%
Data input .............................. By the serial input function (16 bits)
Coloring
Background coloring (composite video signal)
Blanking
Total blanking (14
✕
18 dots)
Border size blanking
Character size blanking
Synchronizing signal
Composite synchronizing signal generation
(PAL, NTSC, M-PAL)
2 output ports (1 digital line)
Oscillation stop function
It is possible to stop the oscillation for synchronizing signal
generation
Built-in half-tone display function
Built-in reversed character display function
Built-in Decoder (NTSC only)
Built-in Encoder (NTSC only)
Built-in synchronous correction circuit
Built-in synchronous separation circuit
Outline 20P4B
CP1
TESTA
CS
←
→
→
↔
→
1
2
3
20
19
18
V
DD1
SCK
SIN
AC
4
5
6
7
17
16
15
14
13
12
11
←
→
←
→
→
→
HOR
CP2
OSCIN
V
SS
P1
P0
TESTB
EDO
V
SS
M35053-XXXFP
V
DD2
CVIDEO
LECHA
CVIN
←
→
→
8
9
10
•
•
•
•
•
•
•
•
•
Outline 20P2Q-A
APPLICATION
TV, VCR, Movie
REV.1.2
MITSUBISHI MICROCOMPUTERS
M35053-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PIN DESCRIPTION
Symbol
OSC1
TESTA
__
Pin name
Clock input
Test pin
Chip select input
Serial clock input
Serial data input/
output
Auto-clear input
Power pin
Composite video
signal output
Character level input
Composite video
signal input
Earthing pin
Encode data output
Test pin
Port P0 output
Port P1 output
Earthing pin
f
SC
input pin for
synchronous signal
generation
Filter output
Horizontal synchro-
nizing signal input
Power pin
Input/
Output
Input
—
Input
Input
Input/
Output
Input
—
Output
This is the filter output pin 1.
Function
This is the pin for test. Connect this pin to GND during normal operation.
This is the chip select pin, and when serial data transmission is being carried out, it goes
to “L”. Hysteresis input. Includes built-in pull-up resistor.
__
CS
SCK
SIN
__
When CS pin is “L”, SIN serial data is taken in when SCK rises. Hysteresis input. Built-in
pull-up resistor is included.
This is the pin for serial input of data and addresses for the display control register and
the display data memory. Also, serially outputs decode data according to the settings in
the relevant registers (serial I/O).
When “L”, this pin resets the internal IC circuit. Hysteresis input. Includes built-in pull-up
resistor.
Please connect to +5V with the analog circuit power pin.
This is the output pin for composite video signals. It outputs 2V
P-P
composite video
signals. In superimpose mode, character output etc. is superimposed on the external
composite video signals from CVIN.
This is the input pin which determines the “white” character color level in the composite
video signal.
This is the input pin for external composite video signals. In superimpose mode, character
output etc. is superimposed on these external composite video signals.
Please connect to GND using circuit earthing pin.
This is the output pin for encode data. It outputs digital three-value data or composite video signals.
This is the pin for test. Connect this pin to GND during normal operation.
This pin outputs the port output or BLNK1 (character background) signal.
This pin outputs the port output or CO1(character) signal.
Please connect to GND using circuit earthing pin (Analog side).
This is the input pin for the sub-carrier frequency (f
SC
) for generating a synchronous
signal.
A frequency of 3.580MHz is needed for NTSC, and a frequency of 4.434MHz in needed
for PAL and 3.576MHz is needed for M-PAL.
Filter output pin 2.
This is the input pin for external composite video signals. This pin inputs the external
video signal clamped sync-chip to 1.5V, and internally carries out synchronous separa-
tion.
Please connect to +5V with the digital circuit power pin.
AC
V
DD2
CVIDEO
LECHA
CVIN
V
SS
EDO
TESTB
P0
P1
V
SS
OSCIN
Input
Input
—
Output
—
Output
Output
—
Input
CP2
HOR
Output
Input
V
DD1
—
2
BLOCK DIAGRAM
CP1
1
19
HOR
CS
Clock oscillation circuit
SYNC-SEP
circuit
3
Decoder circuit
Data slicer
circuit
SCK
4
H counter
3.580MHz(NTSC)
4.434MHz(PAL)
3.576MHz(M-PAL)
17
18
SIN
5
I/O control circuit
Oscillation circuit
for synchronizing
signal generation
OSCIN
CP2
Display location
detection circuit
Timing
generator
Timing
generator
Data
control
circuit
Address
control
circuit
TESTA
2
TESTB
13
Display control
register
Reading address
control circuit
8
10
CVIDEO
CVIN
V
DD1
20
Display RAM
Display control
circuit
NTSC
PAL
M-PAL
video output
circuit
9
12
LECHA
EDO
Shift register
AC
6
V
SS
11
Display character ROM
Blinking circuit
V
SS
16
Port output
circuit
14
15
P0
P1
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
MITSUBISHI MICROCOMPUTERS
V
DD2
7
M35053-XXXSP/FP
3
MITSUBISHI MICROCOMPUTERS
M35053-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
MEMORY CONSTITUTION
Address 00
16
to EF
16
are assigned to the display RAM, address F0
16
to F8
16
are assigned to the display control registers.
The internal circuit is reset and all display control registers (address
F0
16
to F8
16
) are set to “0”
__
display RAM (address 00
16
to EF
16
)
and
are RAM erased when the AC pin level is “L”.
Bit
DAF DAE DAD DAC DAB DAA DA9
Address
00
16
0
0
0
REV BLINK EC2
Reversed
Blinking
character
Set “0” in any of bits DAD through DAF of addresses 00
16
through
EF
16
, and of bits DAE and DAF of addresses F0
16
through F8
16
.
TESTn (n : a number) is MITSUBISHI test memory, so be sure to
observe the setting conditions.
DA8 DA7 DA6
C7
C6
DA5
C5
DA4
C4
DA3
C3
DA2
C2
DA1
C1
DA0
C0
Remarks
EC1 EC0
Encode data or
character color
EC1
EC0
C7
C6
C5
Character code
C4
C3
C2
C1
C0
Display RAM
EF
16
F0
16
F1
16
F2
16
F3
16
F4
16
F5
16
F6
16
F7
16
F8
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REV BLINK EC2
____
___
___
TEST25 W/R TEST11 TEST10 DECB1 DECB0 SYSEP1 SYSEP0 SEPV1 SEPV0 PTD1 PTD0 PTC1 PTC0 Port output specify and so on
TEST26 DVP4 DVP3 DVP2 DVP1 DVP0
TEST27 EVP4 EVP3 EVP2 EVP1 EVP0
___
HP7
VP7
HP6
VP6
HP5
VP5
HP4
VP4
HP3
VP3
HP2
VP2
HP1
VP1
HP0
VP0
TEST28 D/V EFLD1 EFLD0 DFLD1 DFLD0 VSZ21 VSZ20 VSZ11 VSZ10 HSZ21 HSZ20 HSZ11 HSZ10
_______
_______
_______
___
__
__
Horizontal display start position and
Decode position specify
Vertical display start position and
Encode position specify
Character size and Encode
E
Decode
specify
TEST29 TEST14 TEST13 SPACE DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0 Display mode specify
TEST30 TEST19 MB/LB TEST17 TEST16 TEST15 EQP PALH MPAL INT/NON N/P BLINK2 BLINK1 BLINK0 Blinking specify and so on
____
____
TEST31 TEST2 TEST1 TEST0 LBLACK LIN24/32 BLKHF
_____
_____
BB
BG
BR
LEVEL0 PHASE2 PHASE1 PHASE0 Raster color specify
BLK1 BLK0 Control display and so on
TEST32 TEST24 RGBON TEST22 CL17/18 CBLINK CURS7 CURS6 CURS5 CURS4 CURS3 CURS2 CURS1 CURS0 Cursor display specify
EX
0 LEVEL1 EHP4 EHP3 EHP2 EHP1 EHP0 RAMERS DSPON STOP1 STOPIN SCOR
0
Fig. 1 Memory constitution (M35053-XXXSP/FP)
4
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