To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a f amily of 4-Mbit static RAMs organized
as 524,288-words by 8-bit, f abricated by Mitsubishi's high-
perf ormance 0.25µm CMOS technology .
The M5M5408B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are
the important design objectiv es.
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP. Two ty pes of TSOPs are av ailable, M5M5408BTP
(normal-lead-bend TSOP) , M5M5408BRT (rev erse-lead-bend
TSOP). These two ty pes TSOPs are suitable f or a surf ace
mounting on double-sided printed circuit boards.
From the point of operating temperature, the f amily is
div ided into two v ersions; "Standard" and "I-v ersion". Those are
·
·
·
·
·
·
·
·
·
·
·
FEATURES
Single +5V power supply
Small stand-by current: 0.4µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 5.5V
All inputs and outputs are TTL compatible.
Easy memory expansion by S#
Common Data I/O
Three-state outputs: OR-tie capability
OE# prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package:
M5M5408BFP: 32 pin 525 mil SOP
M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
PART NAME TABLE
Version,
Operating
temperature
Part name
(## stands f or
"FP","TP",and "RT")
M5M5408B## -55H
M5M5408B## -70H
M5M5408B## -55HI
M5M5408B## -70HI
Power
Supply
5.0V
5.0V
Access
time
Stand-by c urrent Icc
(PD)
, Vcc=3.0V
ty pical *
25°C
0.4µA
0.4µA
25°C
1µA
1µA
Limit s (max.)
70°C
15µA
15µA
85°C
---
30µA
max.
55ns
70ns
55ns
70ns
Activ e
current
Icc1
(5.0V, ty p.*)
50mA
(10MHz)
25mA
(1MHz)
Standard
0 ~ +70°C
I-
v ersion
-40 ~ +85°C
*Ty pical v alues are sampled, and are not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
17
W#
A
13
A
8
A
9
A
11
OE#
A
10
S#
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
A
15
A
17
W#
A
13
A
8
A
9
A
11
OE#
A
10
S#
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
Pin
A0 ~ A18
S# ( S )
W# ( W )
OE# (OE)
Vcc
GND
Function
Address input
Chip select input
Write control input
Output inable input
Power supply
Ground supply
DQ1 ~ DQ8 Data input / output
Outline
32P2M-A (FP)
32P3Y-H (TP)
Outline
32P3Y-J (RT)
1
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT is organized as 524,288-words
by 8-bit. These dev ices operate on a single +5.0V power
supply , and are directly TTL compatible to both input and
output. Its f ully s t atic circuit needs no clocks and no
ref resh, and makes it usef ul.
A write operation is executed during the S# low and W#
low ov erlap time. The address(A0~A18) must be set up
bef ore the write cy c le
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while S# are in an activ e
state (S#=L).
When setting S# at a high lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips. Setting
the OE# at a high lev el,the output stage is in a high-
impedance state, and the data bus contention problem in
the write cy c le is eliminated.
The power supply c urrent is reduced as low as 0.4µA
(25°C, ty pical), and the memory data can be held at +2V
power supply , enabling battery back-up operation during
power f ailure or power-down operation in the non-selected
mode.
Pin
Mode
Non selection
Write
Read
DQ
High-impedance
Data input (D)
Data output (Q)
Icc
Standby
Activ e
Activ e
Activ e
A0 ~ A18
S# ( S )
W# ( W )
OE# (OE)
Vcc
GND
Function
Address input
Chip select input
Write control input
Output inable input
Power supply
Ground supply
FUNCTION TABLE
S#
H
L
L
L
W#
X
L
H
H
OE#
X
X
L
H
DQ1 ~ DQ8 Data input / output
High-impedance
Read
note: "H" and "L" in this table mean VIH and VIL, respectiv ely .
"X" in this table should be "H" or "L".
BLOCK DIAGRAM
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
A
18
A
15
A
10
A
11
A
9
A
8
A
13
8
7
6
5
4
3
2
30
1
31
13
14
15
MEMORY ARRAY
524288 WORDS
x 8 BITS
17
18
19
20
21
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
23
25
26
27
28
29
22
24
CLOCK
GENERATOR
W#
S#
OE#
V
CC
(5V)
A
0
A
1
A
2
A
3
12
11
10
9
32
16
GND
(0V)
2
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply v oltage
Input v oltage
Output v oltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Standard
I-v
ersion
Ratings
Units
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.3
*
~ +7
-0.3
*
~ Vcc + 0.3
0 ~ Vcc
700
0 ~ +70
-40 ~ +85
-65 ~ +150
V
mW
°
C
°
C
* -3.0V in case of AC (Pulse width _ 30ns)
<
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
High-lev el input v oltage
Low-lev el input v oltage
Conditions
( Vcc= 5V ±10%, unless otherwise noted)
Limits
Min
Ty p.
Max
Vcc+0.3V
Units
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Icc
1
Icc
2
Icc
3
Icc
4
I
OH
= -1mA
High-level output voltage 2
I
OH
= -0.1mA
Low-lev el output v oltage
I
OL
=2mA
V
I
=0
~
Vcc
Input leakage current
High-level output voltage 1
2.2
-0.3 *
2.4
Vcc-0.5V
0.8
V
0.4
±1
±1
µA
Output leakage current
Activ e supply c urrent
(CMOS-lev el input)
S# = V
IH
or OE# =V
IH
, V
I/O
= 0 ~ Vcc
S# _ 0.2V, output-open
<
_
Other inputs < 0.2V or _ Vcc-0.2V
>
f =10MHz
f =1MHz
f =10MHz
f =1MHz
Standard
I-v
ersion
Activ e supply c urrent
S# =V
IL
, output-open
Other inputs= V
IH
or V
IL
(TTL-lev el input)
Stand by s upply current Vcc =5.5V, max.
(CMOS-lev el input)
_
S# > Vcc-0.2V,other inputs=0~Vcc
Stand by s upply current
(TTL-lev el input)
S# =V
IH
, other inputs= 0 ~ Vcc
-
-
-
-
-
-
-
50
25
60
30
1.0
1.0
-
80
30
90
40
30
60
3
mA
µA
mA
Note 1: Direction f or current f lowing into IC is indicated as positiv e (no mark).
Note 2: Ty pical v alues are sampled at Vcc=5.0V and Ta=25°C,
and are not 100% tested.
_
* -3.0V in case of AC (Pulse width <30ns)
CAPACITANCE
Symbol
Parameter
Input capacitance
Output capacitance
Conditions
(Vcc=5.0V±10%, unless otherwise noted)
Limits
Min
Ty p.
Max
Units
C
I
C
O
V
I
=GND, V
I
=25mVrms, f =1MHz
V
O
=
GND,V
O
=25mVrms, f =1MHz
8
10
pF
3
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
Input pulse
Input rise time and f all time
Ref erence lev el
5.0V
(Vcc=5.0V±10%, unless otherwise noted)
VIH=2.4V,VIL=0.6V (-70H, -70HI)
VIH=3.0V,VIL=0V (-55H, -55HI )
5ns
VOH=VOL=1.5V
Transition is measured ±500mV f rom
steady state voltage f or t
en
and t
dis
.
Fig.1, CL=100pF (-70H, -70HI)
CL=30pF (-55H, -55HI )
CL=5pF (f or t
en
,t
dis
)
1.8kΩ
DQ
C
L
990Ω
Output loads
C
L
Includes scope and jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
Parameter
Read cy cle time
Address access time
Chip select access time
Output enable access time
Output disable time af t er S# high
Output disable time af t er OE# high
Output enable time af ter S# low
Output enable time af ter OE# low
Data v alid time after address
-55H, -55HI
Min
Max
-70H, -70HI
Min
Max
Units
t
CR
t
a
(A)
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
55
55
55
25
20
20
10
5
10
70
70
70
35
25
25
10
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
Write cy cle time
Write pulse width
Address set up time
Address set up time with respect to W# high
-55H, -55HI
Min
Max
-70H, -70HI
Min
Max
Units
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
55
40
0
50
50
25
0
0
20
20
5
5
70
50
0
60
60
30
0
0
25
25
5
5
Chip select set up time
Data set up time
Data hold time
Write recov ery time
Output disable time af t er W# low
Output disable time af t er OE# high
Output enable time af ter W# high
Output enable time af ter OE# low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
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