HYM7V75A200D F-Series
Unbuffered 2Mx72 bit SDRAM MODULE
based on 2Mx8 SDRAM, LVTTL, 4K-Refresh
DESCRIPTION
The HYM7V75A200D is high speed 3.3Volt CMOS Synchronous DRAM module consisting of nine 2Mx8
bit Synchronous DRAMs in 44-pin TSOPII and one 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy
circuit board. One 0.33µF and one 0.1µF decoupling capacitors are mounted for each SDRAM.
The HYM7V75A200D is a gold plated socket type Dual In-line Memory Module suitable for easy
interchange and addition of 16M byte memory. All inputs and outputs are synchronized with the rising edge
of the clock input. The data paths are internally pipelined to achieve very high band width. All input and
output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of
consecutive read of write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page),
and the burst count sequence(sequential or interleave). A burst of read of write cycles in progress can be
terminated by a burst terminate command of can be interrupted and replaced by a new burst read or write
command on any cycle. (This pipelined design is not restricted by a ‘ 2N’ rule.)
FEATURES
•
•
•
•
•
•
168Pin Unbuffered DIMM, JEDEC standard
Serial Presence Detect with EEPROM
Single 3.3V±0.3V power supply
All module pins are LVTTL compatible
4096 refresh cycles / 64ms
All inputs and outputs referenced to positive
edge of system clock
•
Auto refresh and self refresh
•
Programmable Burst Length and Burst Type
- 1,2,4,8 and full page for Sequential Burst
- 1,2,4 and 8 for Interleave type
•
Programmable /CAS latency ; 1,2,3 clocks
ORDERING INFORMATION
Part No.
HYM7V75A200DTFG -8
HYM7V75A200DTFG -10P
HYM7V75A200DTFG -10S
Max.
Frequency
125MHz
100MHz
100MHz
Power
Normal
Normal
Normal
PCB
height
1.25
1.25
1.25
Package
TSOPII
TSOPII
TSOPII
Based Comp. Part No
HY57V168010DTC-8
HY57V168010DTC-10P
HY57V168010DTC-10S
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / JUN 1998
HYM7V75A200D F-Series
PIN DESCRIPTION
Pin
CK0 - CK3
Clock
Pin Name
Description
System Clock Input; All other inputs are referenced to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend,
or self refresh.
Select either one of dual banks during both /RAS and /CAS
activity.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command input enable or mask except CLK, CKE and DQM
CKE0
Clock Enable
BA0
Bank Address
A0-A10
/S0, /S2
Address
Chip Select
Row Address
Strobe,Column Address
Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Error check Data
Input/Output
Power Supply/Ground
Write Protection
Serial Presence Detect
Data
Serial Presence Detect
Clock
Serial Presence Detect
Address
/RAS, /CAS,
/WE
DQMB0-7
DQ0-DQ63
CB0-CB7
V
CC
/ V
SS
WP
SDA
SCL
SA0-SA2
/RAS, /CAS and /WE define the operation.
DQM control output buffer in read mode and mask input data
in write mode
Multiplexed data input / output pin
Multiplexed data input / output pin
Power supply for internal circuit and input buffer
EEPROM Write Protection
EEPROM Serial Presence Detect Data Input / Output pin
EEPROM Serial Presence Detect Clock input
EEPROM Serial Presence Detect Address input
Rev. 01
2
HYM7V75A200D F-Series
.
SERIAL PRESENCE DETECT
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
NOTE
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
# of Byte Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time
@ /CAS Latency=3
8 part
10P part
10S part
SDRAM Access Time from Clock
@ /CAS Latency=3
128 Bytes
256 Bytes
SDRAM
11
9
1 Bank
72 Bits
-
LVTTL
8ns
10ns
10ns
6ns
ECC
15.625µs
/ Self Refresh
Supported
80h
08h
04h
0Bh
09h
01h
48h
00h
01h
80h
A0h
A0h
60h
02h
80h
1
1
DIMM Configuration Type
Refresh Rate/Type
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back
Random Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
( Non Buffered and Registered )
SDRAM Module Attributes General
( Burst read, Single bit write, Precharge All,
Auto Precharge )
x8
ECC
tCCD=1 CLK
1,2,4,8,Full Page
2 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
-
08h
08h
01h
8Fh
02h
06h
01h
01h
00h
0Eh
Note:
1. The bank address is excluded.
5
Rev. 0.1
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