TLP116A
TOSHIBA PHOTOCOUPLER
GaAℓAs IRED & PHOTO-IC
TLP116A
Plasma Display Panels (PDPs)
High-Speed Interface
Factory Automation (FA)
The Toshiba TLP116A mini-flat coupler is a small-outline coupler suitable for
surface-mount assembly. The TLP116A consists of a GaAℓAs light-emitting
diode and an integrated high-gain, high-speed photodetector. This unit is
housed in the 6-pin SO package and guarantees a creepage distance of ≥
5.0mm, a clearance of ≥ 5.0mm and an insulation thickness of ≥ 0.4mm.
Therefore, the TLP116A meets the reinforced insulation class requirements of
international safety standards.
Unit: mm
6
5
4
1
3
7.0
±
0.4
0.1 2.1
±
0.1
3.7
±
0.15
4.55
± 0.15
0.4
1.27
2.54
0.15
Inverter logic (totem-pole output)
SO6 package
Guaranteed performance over: −40 to 100°C
Power supply voltage: 4.5 to 5.5V
Input thresholds current: IFHL = 5 mA (max)
Propagation delay time (tpHL / tpLH): 60 ns (max)
Switching speed: 20 MBd (typ.)
Common-mode transient immunity: 10 kV/
μ
s
Isolation voltage: 3750 Vrms
UL approval: UL1577, File No.E67349 Under application
cUL approved :CSA Component Acceptance Service
No. 5A, File No.E67349
Factory
3
SHIELD
0.5 min
TOSHIBA
11−4L1
Weight: 0.08 g (typ.)
Pin Configuration (Top View)
1
VCC
6
5
1: ANODE
3: CATHODE
4: GND
5: V
O
(Output)
6: V
CC
GND
4
CQC approved:GB4943.1,GB8898 Japan
仅适用干海拔
2000m
以下地区安全½用
Option (V4) VDE
approved : DIN EN60747-5-5 ,EN60065,EN60950-1 (Note1)
EN62368-1(Pending)
(Note1)
Note
1
: When a EN60747-5-5 approved type is needed,
please designate “Option(V4)”
Schematic
I
F
I
CC
6
Tr1
I
O
Tr2
5
V
O
V
CC
Truth Table
Input
H
L
LED
ON
OFF
Tr1
OFF
ON
Tr2
ON
OFF
Output
L
H
1＋
VF
3－
SHIELD
4
GND
Construction Mechanical Rating
Creepage Distance: 5.0mm (min)
Clearance:
5.0mm (min)
Insulation Thickness: 0.4mm (min)
A bypass capacitor of 0.1μF must be
connected between pins 6 and 4.
Start of commercial production
1
2008-07
2017-05-26
TLP116A
Absolute Maximum Ratings (Ta=25°C)
Characteristic
Forward current
Forward current derating
LED
Reverse voltage
Input power dissipation
Input power dissipation derating
Output current
DETECTOR
Output current derating
Output voltage
Supply voltage
Output power dissipation
Operating temperature range
Storage temperature range
Lead solder temperature(10 s)
Isolation voltage (AC,60 s, R.H. ≤ 60%)
(Note 2)
(Ta ≥ 85°C)
(Ta ≥ 85°C)
(Ta ≥ 85°C)
(Note 1)
Peak transient forward current
Symbol
IF
ΔI
F
/ °C
IFPT
VR
P
D
ΔP
D
/°C
IO
ΔIO/°C
VO
VCC
PO
Topr
Tstg
Tsol
BVs
Rating
20
−0.5
1
5
40
-1.0
10
-0.25
6
6
40
−40 to 100
−55 to 125
260
3750
Unit
mA
mA/°C
A
V
mW
mW/°C
mA
mA/°C
V
V
mW
°C
°C
°C
Vrms
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba
Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1 : Pulse width PW ≤ 1μs, 300 pps.
Note 2 :This device is regarded as a two terminal device : pins 1 and 3 are shorted together, as are pins 4,5 and 6.
Recommended Operating Conditions
Characteristic
Input current
Supply voltage
Operating temperature
ON
Input voltage , OFF
Symbol
IF(ON)
VF(OFF)
VCC
Topr
Min
8
0
4.5
-40
Typ.
Max
18
0.8
5.5
100
Unit
mA
V
V
°C
—
—
5.0
—
Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the
device. Additionally, each item is an independent guideline respectively. In developing designs using this
product, please confirm specified characteristics shown in this document.
Note:
The detector of this product requires a power supply voltage (V
CC
) of 4.5 V or higher for stable operation.
If the V
CC
is lower than this value, an I
CC
may increase, or an output may be unstable.
Be sure to use the product after checking the supply current, and the operation of a power-on/-off.
Correlation between Input current, switching speed and drive circuit
(reference information).
Input current
(IF)
12mA
8mA
8mA
Test Circuit
1
(Page 4)
1
(Page 4)
2
(Page 4, With Speed up capacitor)
Typical switching speed
21 to 23 MBd
18 to 20 MBd
23 to 27 MBd
2
2017-05-26
TLP116A
Electrical Characteristics
(Unless otherwise specified, Ta=-40 to 100°C, V
CC
=4.5 to 5.5 V )
Characteristic
Input forward voltage
Temperature coefficient
of forward voltage
Input reverse current
Capacitance between Input
terminals
Logic low output voltage
Logic high output voltage
Logic low supply current
Logic high supply current
Input current logic low
output
Input voltage logic high
output
Symbol
VF
ΔVF /ΔTa
IR
CT
VOL
VOH
ICCL
ICCH
IFHL
VFLH
Test
Circuit
Conditions
IF = 10 mA ,Ta = 25°C
IF = 10 mA
VR=5 V, Ta = 25°C
VF = 0 V, f= 1 MHz, Ta = 25°C
IOL = 1.6 mA,
IF = 12 mA, VCC = 5 V
IOH = −0.02 mA,
VF = 1.05 V, VCC = 5 V
IF = 12 mA
VF = 0 V
IO = 1.6 mA, VO < 0.4 V
IO = -0.02 mA, VO > 4.0 V
Min
1.45
Typ.
1.58
-2.0
Max
1.85
Unit
V
mV/°C
μA
pF
V
V
mA
mA
mA
V
—
—
—
—
1
2
3
4
—
—
—
—
4.0
—
10
—
60
—
0.4
—
—
—
—
—
—
—
5.0
5.0
5
—
—
—
0.8
—
—
—
*
All typical values are at Ta=25°C, VCC=5 V, IF(ON)=12 mA unless otherwise specified
Isolation Characteristics
(Ta = 25°C)
Characteristic
Capacitance input to output
Isolation resistance
Symbol
C
S
R
S
BV
S
Test Conditions
Vs = 0 V,f = 1 MHz
R.H. ≤ 60%, V
S
= 500 V
AC, 60 s
Isolation voltage
AC, 1 s, in oil
DC, 60 s, in oil
(Note 1)
Min
―
12
Typ.
0.8
10
14
Max
―
―
―
―
―
Unit
pF
Ω
V
rms
Vdc
(Note 1) 1×10
3750
―
―
―
10000
10000
Note 1:A ceramic capacitor(0.1
μF)
should be connected from pin 6 to pin 4 to stabilize the operation of the high
gain linear amplifier. Failure to provide the bypass may impair the switching property.
The total lead length between capacitor and coupler should not exceed 1 cm.
3
2017-05-26
TLP116A
Switching Characteristics
(Unless otherwise specified, Ta=-40 to 100°C, VCC=4.5 to 5.5 V)
Characteristic
Propagation delay time
to logic high output
Propagation delay time
to logic low output
Propagation delay time
to logic high output
Propagation delay time
to logic low output
Switching time dispersion
between ON and OFF
Output fall time(90-10%)
Output rise time(10-90%)
Common mode transient
immunity at high Level
output
Common mode transient
immunity at low level
output
*All typical values are at Ta=25°C
Note 1: CL is approximately 15 pF which includes probe and Jig/stray wiring capacitance.
CML
CMH
7
VCM = 1000 Vp-p, IF = 12 mA,
Vo(Max) = 0.4 V, Ta = 25°C
-10000
Symbol
tpHL
5
tpLH
tpHL
6
tpLH
|tpHL-
tpLH|
tf
5
IF = 12→0 mA
V
IN
= 0→5 V
(IF = 0→8 mA)
V
IN
= 5→0 V
(IF = 8→0 mA)
Test
Circuit
Conditions
IF = 0→12 mA
R
IN
= 100
Ω
CL = 15 pF
(Note 1)
R
IN
= 470
Ω
C
IN =
27 pF
CL = 15 pF
(Note 1)
Min
Typ.
Max
60
60
60
60
30
Unit
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
10000
—
—
—
—
—
15
15
CL =v15 pF (Note 1)
IF = 0→12 mA
IF = 12→0 mA
IF = 12 mA , R
IN
= 100
Ω,
R
IN
= 100
Ω
CL = 15 pF
(Note 1)
—
—
—
tr
VCM = 1000 Vp-p, IF = 0 mA,
Vo(Min) = 4 V, Ta = 25°C
—
V/μs
—
—
V/μs
TEST CIRCUIT 1
: VOL
I
F
→
TEST CIRCUIT 2
: VOH
VCC
6
5
0.1
μF
1
1
VCC
6
5
V
V
O
↑
I
OH
V
CC
↑
3
SHIELD
GND 4
V
OL
V
I
OL
↑
V
CC
3
SHIELD
GND
4
0.1
μF
VOH = VCC - VO
TEST CIRCUIT 3: ICCL
I
F
→
TEST CIRCUIT 4: ICCH
VCC
6
5
I
CCL
A
0.1
μF
1
1
VCC
6
5
I
CCH
A
0.1
μF
↑
V
CC
3
SHIELD
GND
V
CC
3
SHIELD
GND
4
4
4
2017-05-26
TLP116A
TEST CIRCUIT 5: tpHL, tpLH
I
F
= 12 mA(P.G)
(f = 5 MHz , duty = 50%
less than tr = tf = 5 ns)
VCC
0.1
μF
INPUT
MONITORING
NODE
Vo
MONITORING
NODE
50%
IF
V
CC
V
O
tf
tr
90%
OH
CL=15 pF
SHIELD
R
IN
=100
Ω
GND
CL = 15 pF
1.5 V
tpHL
tpLH
V
10%
VOL
CL is capacitance of the probe and JIG.
(P.G): Pulse Generator
TEST CIRCUIT 6: tpHL, tpLH
V
IN
= 5 V(P.G)
(f = 5 MHz , duty = 50%
less than tr = tf = 5 ns)
INPUT MONITORING NODE
VCC
0.1
μF
Vo
MONITORING
NODE
CL=15 pF
50%
IF
V
CC
C
IN
=27 pF
SHIELD
R
IN
=470
Ω
GND
CL=15 pF
V
O
tf
tr
90%
OH
V
1.5 V
CL is capacitance of the probe and JIG.
(P.G): Pulse Generator
tpHL
tpLH
10%
VOL
TEST CIRCUIT 7: Common-Mode Transient Immunity Test Circuit
90%
SW
A
B
3
SHIELD
V
CM
1000 V
I
F
→
1
6
VCC
5
GND
4
0.1
μF
V
O
V
CC
・SW
B : IF=0 mA
4V
0.4 V
・SW
A : IF=12 mA
CM
L
10%
tr
tf
CM
H
CM
H
=
800(
V
)
t r
(
µ
s
)
CM
L
=
800(
V
)
t f
(
µ
s
)
5
2017-05-26
FPGA/CPLD
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