REJ09B0212-0100Z
8
3804 Group (Spec. H)
User’s Manual
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.00
Revision date: Jan 14, 2005
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
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grams, algorithms, or circuit application examples contained in these materials.
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REVISION HISTORY
Rev.
Date
Page
1.00
Jan 14, 2005
–
First edition issued
3804 Group (Spec. H) User’s Manual
Description
Summary
(1/1)
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
q
CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
q
CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
q
CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0
0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address : 003B
16
]
b
0
1
2
3
4
5
6
7
Stack page selection bit
Name
Processor mode bits
b1
b0
Functions
0 0 : Single-chip mode
01:
1 0 : Not available
11:
0 : 0 page
1 : 1 page
At reset
R W
0
0
0
0
0
0
✕
✕
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.
”
Main clock division ratio selection
bits
0 0 :
φ
= X
IN
/2 (High-speed mode)
0 1 :
φ
= X
IN
/8 (Middle-speed mode)
1 0 :
φ
= X
IN
/8 (Middle-speed mode)
1 1 :
φ
= X
IN
(Double-speed mode)
b7 b6
1
0
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1:
Contents immediately after reset release
0 •••••• “0” at reset release
1 •••••• “1” at reset release
Undefined •••••• Undefined or reset release
✻
••••••Contents determined by option at reset release
2:
Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read
disabled
W••••••Write
••••••Write enabled
✕
••••••Write disabled
3. Supplementary
For details of related development tools and documents, refer to web page “3804 Group” on our website
(http://www.renesas.com/eng/products/mpumcu/8bit/38000/index.html).
Table of contents
3804 Group (Spec.H)
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
PIN CONFIGURATION .................................................................................................................. 1-3
FUNCTIONAL BLOCK .................................................................................................................. 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Size ............................................................................................................................. 1-7
Packages ................................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
CENTRAL PROCESSING UNIT (CPU) ................................................................................. 1-8
MEMORY ................................................................................................................................. 1-13
I/O PORTS .............................................................................................................................. 1-15
INTERRUPTS .......................................................................................................................... 1-23
TIMERS ................................................................................................................................... 1-27
SERIAL INTERFACE ............................................................................................................. 1-40
PULSE WIDTH MODULATION (PWM) ................................................................................ 1-54
A/D CONVERTER .................................................................................................................. 1-56
D/A CONVERTER .................................................................................................................. 1-58
WATCHDOG TIMER .............................................................................................................. 1-59
MULTI-MASTER I
2
C-BUS INTERFACE ............................................................................... 1-60
RESET CIRCUIT .................................................................................................................... 1-74
CLOCK GENERATING CIRCUIT ......................................................................................... 1-76
FLASH MEMORY MODE ...................................................................................................... 1-80
NOTES ON PROGRAMMING ..................................................................................................... 1-99
NOTES ON USAGE ................................................................................................................... 1-100
FUNCTIONAL DESCRIPTION SUPPLEMENT ....................................................................... 1-101
Interrupt ................................................................................................................................. 1-101
Timing After Interrupt ........................................................................................................... 1-102
A/D Converter ....................................................................................................................... 1-103
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Port Pi pull-up control register ..................................................................................... 2-5
2.1.4 Terminate unused pins .................................................................................................. 2-5
2.1.5 Notes on I/O port ........................................................................................................... 2-6
2.1.6 Termination of unused pins .......................................................................................... 2-7
2.2 Interrupt ................................................................................................................................... 2-8
2.2.1 Memory map ................................................................................................................... 2-8
2.2.2 Relevant registers .......................................................................................................... 2-8
2.2.3 Interrupt source ............................................................................................................ 2-12
2.2.4 Interrupt operation ........................................................................................................ 2-13
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
i
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