PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
2M x 36/4M x 18/1M x 72 Flow-through
SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Supports 133-MHz bus operations
• 2M × 36/4M × 18/1M × 72 common I/O
• Fast clock-to-output times
— 5.5 ns (for 150-MHz device)
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
•
•
•
•
•
•
— 8.5 ns (for 100-MHz device)
Single 3.3V –5% and +5% power supply V
DD
Separate V
DDQ
for 3.3V or 2.5V
Clock Enable (CEN) pin to suspend operation
Burst Capability–linear or interleaved burst order
Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1471V33 and CY7C1473V33)
165-ball FBGA and 209-ball BGA(CY7C1475V33)
packages are offered by opportunity basis. (Please
contact Cypress sales or marketing
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
, and CE
3
), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWS
a
, BWS
b
,
BWS
c
, BWS
d
, BWS
e
, BWS
f
, BWS
g
, BWS
h
), and Read-Write
control (WE). BWS
c
and BWS
d
apply to CY7C1471V33 and
CY7C1475V33 only. BWS
e
, BWS
f
, BWS
g
, and BWS
h
apply to
CY7C1475V33 only.
A Clock Enable (CEN) pin allows operation of the
CY7C1471V33, CY7C1473V33, and CY7C1475V33 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is HIGH and the internal device registers
will hold their previous values.
There are three Chip Enable (CE
1
, CE
2
, CE
3
) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after chip is deselected or a
Write cycle is initiated.
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
have an on-chip two-bit burst counter. In the burst mode,
CY7C1471V33, CY7C1473V33, and CY7C1475V33 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequences. The ADV/LD signal is used to
load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
SRAMs are designed to eliminate dead cycles when transi-
tions from Read to Write or vice versa. These SRAMs are
optimized for 100 percent bus utilization and achieves Zero
Bus Latency. They integrate 2,097,152 × 36/4,194,304 × 18/
1,048,576 × 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
BWS
X
CE3
WE
CONTROL
and Write
LOGIC
D
Data-In REG.
Q
A
X
DQ
X
DP
X
X = a, b,
2M × 36
X = 20:0 X = a, b, X= a, b, c, d
c, d
c, d
BWS
x
Mode
2M × 36/
4M × 18/
1M × 72
MEMORY
ARRAY
DQ
x
DP
x
4M × 18
X = 21:0 X = a, b X = a, b X = a, b
X = a, b, X = a, b,
1M × 72
X = 19:0 X = a, b,
c,d,e,f,g,h c,d,e,f,g,h c,d,e,f,g,h
OE
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 27, 2003
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