M1425-PL84C datasheet, PDF - EEWORLD Datasheet

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M1425-PL84C: DescriptionField Programmable Gate Array, 2500 Gates, 125MHz, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size106KB，20 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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M1425-PL84C Overview

Field Programmable Gate Array, 2500 Gates, 125MHz, CMOS, PQCC84, PLASTIC, LCC-84

M1425-PL84C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	PLASTIC, LCC-84
Reach Compliance Code	compliant
Other features	MAX 70 I/OS; MASK BASED
maximum clock frequency	125 MHz
Combined latency of CLB-Max	1.5 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	3
Equivalent number of gates	2500
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2500 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.3116 mm
Base Number Matches	1

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Actel

Mask Programmed Gate Arrays

Fe atur es

• Available in commercial or industrial temperature ranges

• PLCC, PQFP, VQFP, and TQFP packages available

• Meets all internal worst-case FPGA performance

specifications

• Lower I/O capacitance than FPGA

• Lower power dissipation than FPGA

D es c ri pt i o n

• Mask Programmed versions of Actel Field Programmable

Gate Arrays (FPGAs)

• Significant cost reduction for medium- to high-volume

applications

• Pin-for-pin compatible with Actel FPGAs

• PCI Local Bus Revision 2 Compliant

• Automatic translation from Actel FPGA netlist to MPGA

• Test vectors generated from customer simulation vectors

• Short lead times for prototype and production devices

• MPGA available for all ACT 1, ACT 2, 1200XL, ACT 3, and

3200DX devices

• Device sizes from 1,200 to 10,000 gates

• Up to 175 user I/Os

Produc t Fami ly Pr ofi l e

Capacity

MPGA

Device

Type

M1010

M1020

M1225

M1240

M1280

M1415

M1425

M1440

M1460

M14100

M3265

M32100

M32140

M32200

M32300

M32400

Gate Array

Equivalent

Gates

1,200

2,000

2,500

4,000

8,000

1,500

2,500

4,000

6,000

10,000

6,500

10,000

14,000

20,000

30,000

40,000

PLD

Equivalent

Gates

3,000

6,000

6,250

10,000

20,000

3,750

6,250

10,000

15,000

25,000

1,600

25,000

35,000

50,000

75,000

100,000

Flip-Flops

(Maximum)

147

273

382

568

998

312

435

706

976

1153

747

1031

1410

1822

2804

3759

The Actel Mask Programmed Gate Array (MPGA) products

are masked versions of the popular Actel FPGA families.

These semi-custom devices offer the customer a design path

that provides significant cost reduction without significant

risk or engineering effort. For medium- to high-volume

applications in which the design is fixed, the Actel FPGA used

for prototyping and initial production can be replaced by the

corresponding MPGA device.

Available Packages

User I/Os

(Maximum)

104

140

100

140

167

175

126

152

176

202

250

288

PLCC

44, 68-pin

44, 68,

84-pin

—

84-pin

—

PQFP

100-pin

100, 144-pin

100, 160,

208-pin

100-pin

100, 160-pin

160-pin

160, 208-pin

208-pin

100, 160-pin

160, 208-pin

208, 240-pin

240-pin

VQFP

80-pin

100-pin

—

100-pin

—

TQFP

—

176-pin

—

176-pin

—

176-pin

—

176-pin

—

S e p t e m b e r 19 9 7

1-389

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