K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb Sync. Pipelined Burst SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
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* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A.
• Operating in commercial and industrial temperature range.
GENERAL DESCRIPTION
The K7A403600B, K7A403200B and K7A401800B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor (ADSP) or address status cache controller
(ADSC) inputs. Subsequent burst addresses are generated
internally in the system′s burst sequence and are controlled
by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403600B, K7A403200B and K7A401800B are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-16
6.0
3.5
3.5
-14
7.2
4.0
4.0
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
128Kx36/32, 256Kx18
MEMORY
ARRAY
ADSP
A0~A16
or A0~A17
ADDRESS
REGISTER
A2~A16
or A2~A17
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
36/32 or 18
-4-
Rev. 2.0 July 2006
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