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KM44C4003CK-5

Description
Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
Categorystorage    storage   
File Size376KB,20 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

KM44C4003CK-5 Overview

Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

KM44C4003CK-5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOJ
package instructionSOJ, SOJ28,.34
Contacts28
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE
Maximum access time50 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-J28
JESD-609 codee0
length18.42 mm
memory density16777216 bit
Memory IC TypeFAST PAGE DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals28
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height3.76 mm
self refreshNO
Maximum standby current0.001 A
Maximum slew rate0.09 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
KM44C4003C, KM44C4103C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for
seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
Part Identification
- KM44C4003C/C-L (5V, 4K Ref.)
- KM44C4103C/C-L (5V, 2K Ref.)
• Fast Page Mode operation
• Four seperate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast paralleltest mode capability
• TTL compatible inputs and outputs
Unit : mW
• Early Write or output enable controlled write
• JEDEC Standard pinout
2K
605
550
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
Active Power Dissipation
Refresh Cycle
4K
-5
-6
495
440
Speed
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
C4003C
C4103C
Refresh
cycle
4K
2K
Refresh period
Normal
64ms
32ms
Refresh Timer
Refresh Control
Row Decoder
Sense Amps & I/O
RAS
CAS0 - 3
W
Control
Clocks
Vcc
Vss
L-ver
128ms
VBB Generator
Data in
Buffer
Performance Range
Speed
-5
-6
Refresh Counter
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
Memory Array
4,194,304 x 4
Cells
DQ0
to
DQ3
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
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