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PSD403A2-70J

Description
Parallel I/O Port, 40 I/O, CMOS, PQCC68,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size2MB,98 Pages
ManufacturerWaferscale Integration Inc.
Download Datasheet Parametric View All

PSD403A2-70J Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

PSD403A2-70J Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Reach Compliance Codeunknown
Maximum access time7e-8 ns
Other featuresGENERAL PURPOSE ZPLD
maximum clock frequency50 MHz
External data bus width16
JESD-30 codeS-PQCC-J68
JESD-609 codee0
Number of I/O lines40
Number of ports5
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply5 V
Certification statusNot Qualified
ROM size (bits)1024 Bits
Maximum standby current0.00002 A
Maximum slew rate45 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
UV erasableN
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
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