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TS88915TCWD/T70

Description
Clock Driver, CMOS, CQCC28,
Categorylogic    logic   
File Size135KB,20 Pages
ManufacturerThomson-CSF Compsants Specific
Download Datasheet Parametric View All

TS88915TCWD/T70 Overview

Clock Driver, CMOS, CQCC28,

TS88915TCWD/T70 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionQCCJ, LDCC28,.5SQ
Reach Compliance Codeunknown
JESD-30 codeS-XQCC-J28
JESD-609 codee0
MaximumI(ol)0.036 A
Number of terminals28
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Base Number Matches1
TS88915T
LOW SKEW CMOS PLL CLOCK DRIVER
3-State 70 and 100 MHz Versions
DESCRIPTION
The TS88915T Clock Driver utilizes a phazed–locked loop
(PLL) technology to lock its low skew outputs’ frequency and
phase onto an input reference clock. It is designed to provide
clock distribution for high performance microprocessors such
as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge,
RAM’s, MMU’s...
MAIN FEATURES
H
Vcc = 5V

5 %
H
MILITARY TEMPERATURE RANGE
H
TS68040 FULL COMPATIBLE
H
FIVE LOW SKEW OUTPUTS
Five Outputs (Q0-Q4) with Output–to–Output skew < 500
ps each being phase end frequency locked to the SYNC
input.
H
ADDITIONAL OUTPUTS
Three additional outputs are available :
– The 2X_Q output runs twice the system ”Q” frequency.
– The Q/2 output runs at 1/2 the system ”Q” frequency.
– The Q5 output is inverted (180° phase shift).
H
TWO SELECTABLE CLOCK INPUTS
– Two selectable CLOCK inputs are available for test or
redundancy purposes.
– Test Mode pin (PLL_EN) provided for low frequency test-
ing.
– All outputs can go into high impedance (3-state) for board
test purpose.
H
INPUT FREQUENCY RANGE FROM 5MHz to 2X_Q
FMAX
H
THREE INPUT/OUTPUT RATIOS
Input/Output phase–locked frequency ratios of 1:2, 1:1 and
2:1 are available.
H
LOW PART-TO-PART SKEW
The phase variation from part–to–part between the SYNC
and FEEDBACK inputs is less than 550 ps (derived from the
t
PD
specification, which defines the part-to-part skew).
H
CMOS AND TTL COMPATIBLE
– All outputs can drive either CMOS or TTL inputs.
– All inputs are TTL-level compatible.
H
LOCK Indicator (LOCK) indicated a phase–locked
state.
R Suffix
PGA 29
Ceramic Pin grid array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
SCREENING / QUALITY
This product is manufactured :
H
based upon the generic flow of MIL–STD–883.
H
or according to TCS standard.
April 1999
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