M62009L/P/FP
Low Power 2 Output System Reset IC with External Input
REJ03D0782-0100
Rev.1.00
Sep 14, 2005
Description
As applications for microcomputers are increasing, a desire has arisen for a RAM backup function. Let us introduce
Renesas new low power dissipation, high-performance system reset IC, which is suitable for such RAM backup.
The M62009, which is a low power dissipation 2-output microcomputer system reset IC, is a 2-output system reset IC
which provides for RAM backup in microcomputers, and reduces power dissipation by using the Bi-CMOS process.
The M62009 considerably reduces the number of components in the reset circuit.
The M62009 performs two-step detection of normal supply voltage and backup supply voltage required for backup
mode. When the supply voltage is switched from normal supply voltage to backup supply voltage the interruption
output, which is one of the two outputs, gives the interruption signal to a microcomputer, in this way, the
microcomputer reduces power dissipation and enters in the backup mode. If the backup supply voltage goes lower than
the voltage required for backup, the reset output (RESET output) which is different from the
INT
output gives the reset
signal (forced reset) to the microcomputer. The interruption signal from the
INT
output recovers the microcomputer
from the backup mode. To recover from reset,
RESET
output is canceled when the specified interval of time (delay
time) elapses after the signal is given from the
INT
output.
Features
•
Bi-CMOS process realizes a configuration of low current dissipating circuits.
I
CC
= 7
µA
(Typ, normal mode, V
CC1
= V
CC2
= 5.0 V)
I
CC
= 5
µA
(Typ, backup mode, V
CC1
= 5.0 V)
I
CC
= 1
µA
(Typ, backup mode, V
CC1
= 2.5 V)
•
Two-step detection of supply voltage
V
CC1
(RESET):
V
S1-1
= 4.0 V (Typ, increase of V
CC1
)
V
S1-2
= 2.0 V (Typ, decrease of V
CC1
)
V
CC2
(INT):
Free setup
•
Two outputs (open drain type)
Reset output (RESET): Forced reset signal output
Interruption output (INT): Output of the signal for interruption processing (output of the switching signal for
backup mode)
•
Three types of outline packages
8-pin plastic SIP (single in-line package)
8-pin plastic DIP (dual in-line package)
8-pin plastic SOP (mini flat package)
•
Output based on RAM backup mode (see the timing chart)
Application
•
Prevention of errors in microcomputer system in electronic equipment that requires RAM backup, such as office,
industrial, and home-use equipment.
Rev.1.00 Sep 14, 2005 page 1 of 6
M62009L/P/FP
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Supply voltage
Output sink current
Power dissipation
Symbol
V
CC
Isink
Pd
Ratings
8
5
800
625
440
Thermal derating
Operating temperature
Storage temperature
Kθ
Topr
Tstg
4.4
–20 to +75
–40 to +125
mW/°C
°C
°C
Unit
V
mA
mW
Conditions
8-pin SIP
8-pin DIP
8-pin SOP
Ta
≥
25°C
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
Item
Detection voltage
Reference voltage
Hysteresis voltage
Circuit current
Symbol
V
S1-1
V
S1-2
V
S2
∆V
S
I
CC1
I
CC2-1
I
CC2-2
t
d
Vsat
t
RESET
t
INT
Min
3.8
1.85
1.23
—
—
—
—
—
—
—
—
Typ
4.0
2.00
1.28
87
7
5
1
50
0.2
30
100
Max
4.2
2.15
1.33
—
15
10
3
—
0.4
—
—
Unit
V
V
mV
µA
Test Conditions
Increase of V
CC1
Decrease of V
CC1
Decrease of V
1
V
CC2
= Detection voltage of hysteresis voltage
(Detection voltage = 4V setup)
V
CC1
= V
CC2
= 5V
V
CC1
= 5V, V
CC2
= 0V
V
CC1
= 2.5V, V
CC2
= 0V
Cd = 0.33µF
V
IN
= 5V, I
O
= 4mA (NMOS)
Time between V
CC1
(when falling) = V
S1-2
and
output of
RESET
signal
Time between V
CC2
(when falling) = V
S2
and
output of
INT
signal
Delay time
Output saturation voltage
Reset output response time
Interruption output reset time
ms
V
µs
µs
Rev.1.00 Sep 14, 2005 page 3 of 6
M62009L/P/FP
Operating Description
V
SH
V
SL
V
SH
V
SL
V
SH
V
SL
V
CC2
INT
(1)
V
S1-1
(2)
(1)
(2)
V
S1-2
(1)
V
S1-1
(2)
V
CC1
V
S1-2
RESET
t
d
t
d
(3)
(4)
(3)
(4)
(1): V
CC2
= V
SH
(increase of V
CC2
)
INT
output
→
Low (V
SH
= V
SL
+
∆V
S
)
(2): V
CC2
= V
SL
(decrease of V
CC2
)
INT
output
→
High (V
SL
=
R
1
+ R
2
V
S2
)
R
2
(3): Delay time obtained from V
S1-1
. td = 50ms (Cd = 0.33µF): t
d
≈
1.52
×
10
5
×
C (s)
RESET
output: reset cancel (cancel)
(4): V
CC1
= V
S1-2
(V
CC1
decrease)
RESET
output: forced reset output (L reset)
Figure 1 Operating Waveform
Application Example
Car Audio
ACC detection
Regulator
5V
PF
Power fail
ACC SW
V
CC1
VDD
detection
BACKUP
detection
RESET
INT
V
DD
Power supply pin
RESET
Reset input
INT
Interrupt input
Microcomputer
R
1
V
CC2
V
1
Cd
Cd
R
2
M62009
Note: Interrupt detection V
SL
is set by resistance R
1
between V
CC2
and V
1
and resistance R
2
between R
1
and V
1
.
V
SL
=
R
1
+ R
2
V
S2
R
2
Figure 2 Application Example
Rev.1.00 Sep 14, 2005 page 4 of 6
FPGA/CPLD
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