H5PS1G83EFR Series
1Gb DDR2 SDRAM
H5PS1G83EFR-xxC
H5PS1G83EFR-xxI
H5PS1G83EFR-xxL
H5PS1G83EFR-xxJ
H5PS1G83EFR-G7x
This document is a general product description and is subject to change without notice. SK Hynix Semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Jun. 2012
1
Release
H5PS1G83EFR Series
Revision Details
Rev.
1.0
1.1
1.2
History
Released
IDD Specification update @1066 IDD update
New revised logo
Draft Date
Aug. 2009
Oct. 2010
Jun. 2012
Hynix to Sk hynix
Remark
Rev. 1.2 / Jun. 2012
2
Release
H5PS1G83EFR Series
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Operating Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions(SSTL_1.8)
3.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC Output Parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 1.2 / Jun. 2012
3
Release
H5PS1G83EFR Series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD = 1.8 +/- 0.1V
VDDQ = 1.8 +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
8 banks
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 60ball FBGA(x8)
Full strength driver option controlled by EMR
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Self-Refresh High Temperature Entry
Rev. 1.2 / Jun. 2012
4
Release
H5PS1G83EFR Series
Ordering Information
Part No. / Status
H5PS1G83EFR-xx*C
H5PS1G83EFR-xx*I
H5PS1G83EFR-xx*L
128Mx8
Configura-
tion
Power Consumption
Normal Consumption
Normal Consumption
Low Power Consumption
(IDD6 Only)
Low Power Consumption
(IDD6 Only)
Operation Temp
Commercial
Industrial
Commercial
60 Ball
fBGA
Package
H5PS1G83EFR-xx*J
Note:
Industrial
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-xxP and xxQ are the low current bin, refer to the IDD specification table.
-
SK Hynix Halogen-free products are compliant to RoHS.
SK Hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materi-
als.
We'll add "R" character after "F" for Lead & Halogen free products
Operating Frequency
Grade
E3
C4
Y5
S6
S5
G7
Note:
-G7
is a special speed product used in electronic engineering for high speed storage of the working data of a consumer
digital electronic device.
tCK(ns)
5
3.75
3
2.5
2.5
1.875
CL
3
4
5
6
5
7
tRCD
3
4
5
6
5
7
tRP
3
4
5
6
5
7
Unit
Clk
Clk
Clk
Clk
Clk
Clk
Rev. 1.2 / Jun. 2012
5
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