K7B403625B
K7B401825B
128Kx36 & 256Kx18 Synchronous SRAM
4Mb Sync. Burst SRAM Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 3.0 July 2006
K7B403625B
K7B401825B
Document Title
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial draft
1. Changed DC parameters
Icc ; from 300mA to 250mA at -65,
from 280mA to 230mA at -75,
from 260mA to 210mA at -80,
from 240mA to 190mA at -90,
Icc ; from 140mA
from 130mA
from 120mA
from 110mA
to
to
to
to
130mA at -65,
120mA at -75,
110mA at -80,
100mA at -90,
Draft Date
May. 15. 2001
June. 12. 2001
Remark
Preliminary
Preliminary
0.2
1.0
I
SB1
; from 100mA to 80mA
1. Add x32 org. and industrial temperature
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
1. Remove x32 organization
2. Remove -80 speed bin
1. Add lead-free package
Aug. 11. 2001
Nov. 15. 2001
Preliminary
Final
2.0
Nov. 17. 2003
Final
3.0
Jul. 3, 2006
Final
-2-
Rev. 3.0 July 2006
K7B403625B
K7B401825B
FEATURES
128Kx36 & 256Kx18 Synchronous SRAM
128Kx36 & 256Kx18-Bit Synchronous Burst SRAM
GENERAL DESCRIPTION
The K7B403625B and K7B401825B are 4,718,592 bits Syn-
chronous Static Random Access Memory designed to support
zero wait state performance for advanced Pentium/Power PC
based system. And with CS
1
high, ADSP is blocked to control
signals.
It can be organized as 128K(256K) words of 36(18) bits. And it
integrates address and control registers, a 2-bit burst address
counter and high output drive circuitry onto a single integrated
circuit for reduced components counts implementation of high
performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B403625B and K7B401825B are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in a 100pin TQFP package. Multiple power and ground
pins are utilized to minimize ground bounce.
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A (Lead and Lead-Free package)
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
CD
t
OE
-65 -75 Unit
7.5
6.5
3.5
8.5
7.5
3.5
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
128Kx36 , 256Kx18
MEMORY
ARRAY
ADSP
A0~A16
or A0~A17
ADDRESS
REGISTER
A2~A16
or A2~A17
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
BUFFER
36 or 18
-4-
Rev. 3.0 July 2006
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