a
FEATURES
Fast Conversion Time: 660 ns Max
100 kHz Track-and-Hold Function
1 MHz Sample Rate
Unipolar and Bipolar Input Ranges
Ratiometric Reference Inputs
No External Clock
Extended Temperature Range Operation
Skinny 20-Lead DlPs, SOIC, and 20-Terminal
Surface-Mount Packages
LC MOS High Speed, P Compatible
8-Bit ADC with Track/Hold Function
AD7821
FUNCTIONAL BLOCK DIAGRAM
2
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7821 is a high speed, 8-bit, sampling, analog-to-digital
converter that offers improved performance over the popular
AD7820. It offers a conversion time of 660 ns (versus 1.36
µs
for the AD7820) and 100 kHz signal bandwidth (versus 6.4
kHz). The sampling instant is better defined and occurs on the
falling edge of
WR
or
RD.
The provision of a V
SS
pin (Pin 19)
allows the part to operate from
±
5 V supplies and to digitize
bipolar input signals. Alternatively, for unipolar inputs, the V
SS
pin
can be grounded and the AD7821 will operate from a single +5 V
supply, like the AD7820.
The AD7821 has a built-in track-and-hold function capable of
digitizing full-scale signals up to 100 kHz max. It also uses a
half-flash conversion technique that eliminates the need to gen-
erate a CLK signal for the ADC.
The AD7821 is designed with standard microprocessor control
signals (CS,
RD, WR,
RDY,
INT)
and latched, three-state data
outputs capable of interfacing to high speed data buses. An
overflow output (OFL) is also provided for cascading devices to
achieve higher resolution.
The AD7821 is fabricated in Linear Compatible CMOS
(LC
2
MOS), an advanced, mixed technology process combining
precision bipolar circuits with low power CMOS logic. The part
features a low power dissipation of 50 mW.
1. Fast Conversion Time
The half-flash conversion technique, coupled with fabrication
on Analog Devices’ LC
2
MOS process, enables a very fast con-
version time. The conversion time for the WR-RD mode is
660 ns, with 700 ns for the RD mode.
2. Built-In Track-and-Hold
This allows input signals with slew rates up to 1.6 V/µs to be
converted to 8 bits without an external track-and-hold. This
corresponds to a 5 V peak-to-peak, 100 kHz sine wave signal.
3. Total Unadjusted Error
The AD7821 features an excellent total unadjusted error figure
of less than
±
1 LSB over the full operating temperature range.
4. Unipolar/Bipolar Input Ranges
The AD7821 is specified for single-supply (+5 V) operation
with a unipolar full-scale range of 0 to +5 V, and for dual-supply
(±5 V) operation with a bipolar input range of
±
2.5 V. Typical
performance characteristics are given for other input ranges.
5. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the
AD7821 is specified for ac parameters, including signal-to-
noise ratio, distortion, and slew rate.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
V
DD
= +5 V 5%, GND = 0 V. Unipolar Input Range: V
SS
= GND, V
REF
(+) = 5 V,
V
REF
(–) = GND. Bipolar Input Range: V
SS
= –5 V 5%, V
REF
(+) = 2.5 V,
V
REF
(–) = –2.5 V. These test conditions apply unless otherwise stated. All specifications T
MIN
to T
MAX
unless otherwise noted. Specifications
apply for RD Mode (Pin 7 = 0 V).
AD7821–SPECIFICATIONS
K Version
1
8
±
1
8
8
±
1
±
1
45
–50
–50
8
±
1
8
8
±
1
±
1
45
–50
–50
Parameter
UNIPOLAR INPUT RANGE
Resolution
2
Total Unadjusted Error
3
Minimum Resolution for which
No Missing Codes are Guaranteed
BIPOLAR INPUT RANGE
Resolution
2
Zero Code Error
Full Scale Error
Signal-to-Noise Ratio (SNR)
3
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
B, T Versions
Unit
Bits
LSB max
Bits
Bits
LSB max
LSB max
dB min
dB max
dB max
Comments
Slew Rate, Tracking
3
REFERENCE INPUT
Input Resistance
V
REF
(+) Input Voltage Range
V
REF
(–) Input Voltage Range
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
LOGIC INPUTS
CS, WR, RD
V
INH
V
INL
I
INH
(CS,
RD)
I
INH
(WR)
I
INL
Input Capacitance
4
MODE
V
INH
V
INL
I
INH
I
INL
Input Capacitance
4
LOGIC OUTPUTS
DB0–DB7,
OFL, INT
V
OH
V
OL
I
OUT
(DB0–DB7)
Output Capacitance
4
(DB0–DB7)
RDY
V
OL
I
OUT
Output Capacitance
4
POWER SUPPLY
I
DD5
I
SS
Power Dissipation
Power Supply Sensitivity
–50
–50
1.6
2.36
1.0/4.0
V
REF
(–)/V
DD
V
SS
/V
REF
(+)
V
REF
(–)/V
REF
(+)
±
3
55
–50
–50
1.6
2.36
1.0/4.0
V
REF
(–)/V
DD
V
SS
/V
REF
(+)
V
REF
(–)/V
REF
(+)
±
3
55
dB max
dB max
V/µs max
V/µs typ
kΩ min/kΩ max
V min/V max
V min/V max
V min/ max
µA
max
pF typ
V
IN
= 99.85 kHz Full-Scale Sine Wave with f
SAMPLING
= 500 kHz
V
IN
= 99.85 kHz Full-Scale Sine Wave with f
SAMPLING
= 500 kHz
V
IN
= 99.85 kHz Full-Scale Sine Wave with f
SAMPLING
= 500 kHz
fa (84.72 kHz) and fb (94.97 kHz) Full-Scale Sine Waves
with f
SAMPLING
= 500 kHz
Second Order Terms
Third Order Terms
–5 V
≤
V
IN
≤
+5 V
2.4
0.8
1
3
–1
8
3.5
1.5
200
–1
8
2.4
0.8
1
3
–1
8
3.5
1.5
200
–1
8
V min
V max
µA
max
µA
max
µA
max
pF max
V min
V max
µA
max
µA
max
pF max
Typically 5 pF
50
µA
typ
Typically 5 pF
4.0
0.4
±
3
8
0.4
±
3
8
20
100
50
±
1/4
4.0
0.4
±
3
8
0.4
±
3
8
20
100
50
±
1/4
V min
V max
µA
max
pF max
V max
µA
max
pF max
mA max
µA
max
mW typ
LSB max
I
SOURCE
= 360
µA
I
SINK
= 1.6 mA
Floating State Leakage
Typically 5 pF
I
SINK
= 2.6 mA
Floating State Leakage
Typically 5 pF
CS
=
RD
= 0 V
CS
=
RD
= 0 V
±
1/16 LSB typ, V
DD
= 4.75 V to 5.25 V,
(V
REF
(+) = 4.75 V max for Unipolar Mode)
NOTES
1
Temperature Ranges are as follows: K Version = –40°C to +85°C; B Version = –40°C to +85°C; T Version = –55°C to +125°C.
2
1 LSB = 19.53 mV for both the unipolar (0 V to +5 V) and bipolar (–2.5 V to +2.5 V) input ranges.
3
See Terminology.
4
Sample tested at +25°C to ensure compliance.
5
See Typical Performance Characteristics.
Specifications subject to change without notice.
–2–
REV. B
AD7821
TIMING CHARACTERISTICS
1
Parameter
t
CSS
t
CSH
t
RDY2
t
CRD
t
ACC03
t
INTH2
t
DH4
t
P
t
WR
t
RD
t
READ1
t
ACC13
t
RI
t
INTL2
t
READ2
t
ACC23
t
IHWR2
t
ID3
160
185
150
380
500
65
65
90
80
30
45
205
235
185
–
610
75
75
110
100
35
60
240
275
220
–
700
85
85
130
120
40
70
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns max
ns max
ns max
ns max
Limit at +25 C
(All Versions)
0
0
70
700
t
CRD
+ 25
t
CRD
+ 50
50
80
15
60
350
250
10
250
160
0
0
85
875
t
CRD
+ 30
t
CRD
+ 65
–
85
15
70
425
325
10
350
205
(V
DD
= +5 V
5%, V
SS
= 0 V or –5 V
Limit at
T
MIN
, T
MAX
(T Version)
0
0
100
975
t
CRD
+ 35
t
CRD
+ 75
–
90
15
80
500
400
10
450
240
5%; Unipolar or Bipolar Input Range)
Limit at
T
MIN
, T
MAX
(K, B Versions)
Unit
ns min
ns min
ns max
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns min
ns min
µs
max
ns min
ns min
Conditions/Comments
CS
to
RD/WR
Setup Time
CS
to
RD/WR
Hold Time
CS
to RDY Delay. Pull-Up
Resistor 5 kΩ
Conversion Time (RD Mode)
Data Access Time (RD Mode)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay (RD Mode)
Data Hold Time
Delay Time Between Conversions
Write Pulsewidth
Delay Time between
WR
and
RD
Pulses
RD
Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by t
ACC1
Data Access Time (WR-RD Mode, see Figure 12b)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay
WR
to
INT
Delay
RD
Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by t
ACC2
Data Access Time (WR-RD Mode, see Figure 12a)
C
L
= 20 pF
C
L
= 100 pF
WR
to
INT
Delay (Stand-Alone Operation)
Data Access Time after
INT
(Stand-Alone Operation)
C
L
= 20 pF
C
L
= 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
Model
1
AD7821KN
AD7821KP
AD7821KR
AD7821BQ
AD7821TQ
AD7821TE
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
Total
Unadjusted Package
Error (LSB) Option
2
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
N-20
P-20A
RW-20
Q-20
Q-20
E-20A
a. High Z to V
OH
b. High Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
a. V
OH
to High Z
b. V
OL
to High Z
Figure 2. Load Circuits for Data Hold Time Test
REV. B
–3–
AD7821
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, + 7 V
Digital Input Voltage to GND
(Pins 6–8, 13) . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(Pins 2–5, 9, 14–18) . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
(+) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
REF
(–) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
IN
to GND . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses
above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7821 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
LCCC
WARNING!
ESD SENSITIVE DEVICE
DIP AND SOIC
PLCC
PIN FUNCTION DESCRIPTIONS
Pin
1
2
3–5
6
7
8
9
10
11
12
13
14–16
17
18
19
20
Mnemonic Description
V
IN
DB0
DB1–DB3
WR/RDY
MODE
RD
INT
GND
V
REF
(–)
V
REF
(+)
CS
DB4–DB6
DB7
OFL
V
SS
V
DD
Analog Input: Range V
REF
(–)
≤
V
IN
≤
V
REF
(+)
Three-State Data Output (LSB)
Three-State Data Outputs
WRITE control input/READY status output. See Digital Interface section.
Mode Selection Input. It determines whether the device operates in the WR-RD or RD mode. This input is internally
pulled low through a 50
µA
current source. See Digital Interface section.
READ Input.
RD
must be low to access data from the part. See Digital Interface section.
INTERRUPT Output.
INT
going low indicates that the conversion is complete.
INT
returns high on the rising
edge of
CS
or
RD.
See Digital Interface section.
Ground
Lower limit of reference span.
Range: V
SS
≤
V
REF
(–)
≤
V
REF
(+).
Upper limit of reference span.
Range: V
REF
(–) < V
REF
(+)
≤
V
DD
.
Chip Select Input. The device is selected when this input is low.
Three-State Data Outputs
Three-State Data Output (MSB)
Overflow Output. If the analog input is higher than (V
REF
(+) – 1/2 LSB),
OFL
will be low at the end of conversion. It
is a non-three-state output which can be used to cascade two or more devices to increase resolution.
Negative Supply Voltage
V
SS
= 0 V; Unipolar Operation
V
SS
= –5 V; Bipolar Operation
Positive Supply Voltage, +5 V
–4–
REV. B
AD7821
TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)
INTERMODULATION DISTORTION
8
An ADC with 8-bit resolution can resolve one part in 2 (1/256
of full scale). For the AD7821 operating in either the unipolar
or bipolar input range with 5 V full scale, one LSB is 19.53 mV.
TOTAL UNADJUSTED ERROR
This is a comprehensive specification which includes relative
accuracy, offset error, and full-scale error.
SLEW RATE
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mfa+nfb, where m, n = 0, 1, 2, 3…. Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), and the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb). For the AD7821 intermodulation distortion is calcu-
lated separately for both the second and third order terms.
SIGNAL-TO-NOISE RATIO (SNR)
Slew rate is the maximum allowable rate of change of input
signal such that the digital sample values are not in error.
TOTAL HARMONIC DISTORTION (THD)
Total harmonic distortion is the ratio of the square root of the
sum of the squares of the rms value of the harmonics to the rms
value of the fundamental. For the AD7821, total harmonic dis-
tortion is defined as
2
2
2
2
2
V
2
+
V
3
+
V
4
+
V
5
+
V
6
20 log
dB
V
1
where
V
1
is the rms amplitude of the fundamental and
V
2
, V
3
, V
4
,
V
5
,
and
V
6
are the rms amplitudes of the individual harmonics.
Signal-to-noise ratio is measured signal-to-noise at the output of
the ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all nonfundamental signals (excluding
dc) up to half the sampling frequency. SNR is dependent on the
number of quantization levels used in the digitization process.
The theoretical SNR for a sine wave input is given by:
SNR
=
(
6.02
N
+
1.76
)
dB
where
N
is the number of bits in the ADC. Thus, for an ideal
8-bit ADC, SNR = 50 dB.
PEAK HARMONIC OR SPURIOUS NOISE
(
)
Peak harmonic or spurious noise is the rms value of the largest
nonfundamental frequency (excluding dc) up to half the sam-
pling frequency to the rms value of the fundamental.
REV. B
–5–
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